| Line 3... |
Line 3... |
vpiHandle DOUT = vpi_handle_by_name("module_tb.TOP_DOUT", NULL);
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vpiHandle DOUT = vpi_handle_by_name("module_tb.TOP_DOUT", NULL);
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vpiHandle SOUT = vpi_handle_by_name("module_tb.TOP_SOUT", NULL);
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vpiHandle SOUT = vpi_handle_by_name("module_tb.TOP_SOUT", NULL);
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vpiHandle DIN = vpi_handle_by_name("module_tb.TOP_DIN", NULL);
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vpiHandle DIN = vpi_handle_by_name("module_tb.TOP_DIN", NULL);
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vpiHandle SIN = vpi_handle_by_name("module_tb.TOP_SIN", NULL);
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vpiHandle SIN = vpi_handle_by_name("module_tb.TOP_SIN", NULL);
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|
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//vpiHandle DTA = vpi_handle_by_name("module_tb.SPW_SC_FSM", NULL);
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vpiHandle DTA = vpi_handle_by_name("module_tb.SPW_SC_FSM", NULL);
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//vpiHandle TX_CLOCK_OUT = vpi_handle_by_name("module_tb.TX_CLOCK_OUT", NULL);
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//vpiHandle TX_CLOCK_OUT = vpi_handle_by_name("module_tb.TX_CLOCK_OUT", NULL);
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|
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vpiHandle i = vpi_handle_by_name("module_tb.i", NULL);
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vpiHandle i = vpi_handle_by_name("module_tb.i", NULL);
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vpiHandle tx_clock = vpi_handle_by_name("module_tb.time_clk_ns", NULL);
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|
|
|
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dout_value.format = vpiIntVal;
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dout_value.format = vpiIntVal;
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sout_value.format = vpiIntVal;
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sout_value.format = vpiIntVal;
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|
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din_value.format = vpiIntVal;
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din_value.format = vpiIntVal;
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sin_value.format = vpiIntVal;
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sin_value.format = vpiIntVal;
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|
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fsm_value.format = vpiIntVal;
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fsm_value.format = vpiIntVal;
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|
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v_generate.format=vpiIntVal;
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v_generate.format=vpiIntVal;
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//fsm_value.format = vpiIntVal;
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fsm_value.format = vpiIntVal;
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//message_value.format = vpiIntVal;
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//message_value.format = vpiIntVal;
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|
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if(SC_TOP->finish_simulation() == 1)
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if(SC_TOP->finish_simulation() == 1)
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{
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{
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v_generate.value.integer = 1;
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v_generate.value.integer = 1;
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| Line 41... |
Line 43... |
vpi_get_value(SOUT, &sout_value);
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vpi_get_value(SOUT, &sout_value);
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vpi_get_value(DOUT, &dout_value);
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vpi_get_value(DOUT, &dout_value);
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SC_TOP->set_rx_sin(sout_value.value.integer);
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SC_TOP->set_rx_sin(sout_value.value.integer);
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SC_TOP->set_rx_din(dout_value.value.integer);
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SC_TOP->set_rx_din(dout_value.value.integer);
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|
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//fsm_value.value.integer = SC_TOP->get_spw_fsm();
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fsm_value.value.integer = SC_TOP->get_spw_fsm();
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//vpi_put_value(DTA, &fsm_value, NULL, vpiNoDelay);
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vpi_put_value(DTA, &fsm_value, NULL, vpiNoDelay);
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|
|
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vpi_get_value(tx_clock, &sout_value);
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|
|
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if(sout_value.value.integer != SC_TOP->verilog_frequency())
|
|
{
|
|
sin_value.value.integer = SC_TOP->verilog_frequency();
|
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vpi_put_value(tx_clock, &sin_value, NULL, vpiNoDelay);
|
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}
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//fsm_value.value.integer = SC_TOP->clock_tx();
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//fsm_value.value.integer = SC_TOP->clock_tx();
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//vpi_put_value(TX_CLOCK_OUT, &fsm_value, NULL, vpiNoDelay);
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//vpi_put_value(TX_CLOCK_OUT, &fsm_value, NULL, vpiNoDelay);
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|
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}
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}
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|
