| Line 55... |
Line 55... |
output ddr3_ce,
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output ddr3_ce,
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output [ 7:0] ddr3_dm,
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output [ 7:0] ddr3_dm,
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|
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output phy_init_done,
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output phy_init_done,
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|
|
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output [ 7:0] fifo_used,
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|
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input dcm_locked,
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input dcm_locked,
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input sysrst
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input sysrst
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);
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);
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|
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wire [255:0] rd_data_fifo_out;
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wire [255:0] rd_data_fifo_out;
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reg [255:0] rd_data_cache;
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reg [ 23:0] rd_addr_cache;
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reg [ 23:0] rd_addr_cache;
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wire [ 71:0] wr_dout;
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wire [ 71:0] wr_dout;
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wire [ 31:0] cmd_out;
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wire [ 31:0] cmd_out;
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reg wb_stb_i_d;
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reg wb_stb_i_d;
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reg [ 31:0] mask_data;
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reg [ 31:0] mask_data;
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|
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wire push_tran;
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wire fifo_read;
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wire fifo_empty;
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wire fifo_empty;
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reg push_tran_d;
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reg fifo_read_d;
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reg fifo_empty_d;
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wire [13:0] parallelterminationcontrol;
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wire [13:0] parallelterminationcontrol;
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wire [13:0] seriesterminationcontrol;
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wire [13:0] seriesterminationcontrol;
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|
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dram dram_ctrl(
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dram dram_ctrl(
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| Line 169... |
Line 164... |
assign trig0[237]=0;
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assign trig0[237]=0;
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assign trig0[238]=0;
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assign trig0[238]=0;
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assign trig0[254:239]=0;
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assign trig0[254:239]=0;
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|
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reg fifo_full_d;
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reg fifo_full_d;
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reg written;
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|
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dram_fifo fifo(
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dram_fifo fifo(
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.aclr(ddr_rst),
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.aclr(ddr_rst),
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|
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.wrclk(wb_clk_i),
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.wrclk(wb_clk_i),
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.rdclk(ddr_clk),
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.rdclk(ddr_clk),
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|
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.data({wb_sel_i,wb_dat_i,wb_we_i,wb_adr_i[33:3]}),
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.data({wb_sel_i,wb_dat_i,wb_we_i,wb_adr_i[33:3]}),
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.wrreq(wb_cyc_i && wb_stb_i && (!wb_stb_i_d || fifo_full_d) && !fifo_full && !(rd_addr_cache==wb_adr_i[28:5] && !wb_we_i)),
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.wrreq(wb_cyc_i && wb_stb_i && (!wb_stb_i_d || (fifo_full_d && !written)) && !fifo_full && !(rd_addr_cache==wb_adr_i[28:5] && !wb_we_i)),
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.wrfull(fifo_full),
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.wrfull(fifo_full),
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|
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.rdreq(fifo_read),
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.rdreq(fifo_read),
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.q({wr_dout,cmd_out}),
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.q({wr_dout,cmd_out}),
|
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.wrusedw(fifo_used),
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.rdempty(fifo_empty)
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.rdempty(fifo_empty)
|
);
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);
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|
|
assign fifo_read=cmd_out[31] ? push_tran:rd_data_valid;
|
`define DDR_IDLE 3'b000
|
|
`define DDR_WRITE_1 3'b001
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reg dram_ready_d;
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`define DDR_WRITE_2 3'b010
|
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`define DDR_READ_1 3'b011
|
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`define DDR_READ_2 3'b100
|
|
|
|
reg [2:0] ddr_state;
|
|
reg push_tran;
|
|
reg fifo_read;
|
|
|
always @(posedge ddr_clk)
|
always @(posedge ddr_clk or posedge ddr_rst)
|
|
if(ddr_rst)
|
begin
|
begin
|
fifo_empty_d<=fifo_empty;
|
ddr_state<=`DDR_IDLE;
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fifo_read_d<=fifo_read;
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fifo_read<=0;
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dram_ready_d<=dram_ready;
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push_tran<=0;
|
fifo_full_d<=fifo_full;
|
rd_data_valid_stb<=0;
|
end
|
end
|
|
else
|
// Push transaction to controller FIFO
|
case(ddr_state)
|
assign push_tran=!fifo_empty && dram_ready && (fifo_empty_d || fifo_read_d || !dram_ready_d);
|
`DDR_IDLE:
|
|
if(!fifo_empty && dram_ready)
|
|
begin
|
|
push_tran<=1;
|
|
if(cmd_out[31])
|
|
begin
|
|
ddr_state<=`DDR_WRITE_1;
|
|
fifo_read<=1;
|
|
end
|
|
else
|
|
ddr_state<=`DDR_READ_1;
|
|
end
|
|
`DDR_WRITE_1:
|
|
begin
|
|
push_tran<=0;
|
|
fifo_read<=0;
|
|
ddr_state<=`DDR_WRITE_2; // Protect against FIFO empty signal latency
|
|
end
|
|
`DDR_WRITE_2:
|
|
ddr_state<=`DDR_IDLE;
|
|
`DDR_READ_1:
|
|
begin
|
|
push_tran<=0;
|
|
if(rd_data_valid)
|
|
begin
|
|
rd_data_valid_stb<=1;
|
|
fifo_read<=1;
|
|
ddr_state<=`DDR_READ_2;
|
|
end
|
|
end
|
|
`DDR_READ_2:
|
|
begin
|
|
fifo_read<=0;
|
|
if(wb_ack_d1) // Enought delay to protect against FIFO empty signal latency
|
|
begin
|
|
rd_data_valid_stb<=0;
|
|
ddr_state<=`DDR_IDLE;
|
|
end
|
|
end
|
|
endcase
|
|
|
reg rd_data_valid_stb;
|
reg rd_data_valid_stb;
|
reg rd_data_valid_stb_d1;
|
reg rd_data_valid_stb_d1;
|
reg rd_data_valid_stb_d2;
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reg rd_data_valid_stb_d2;
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reg rd_data_valid_stb_d3;
|
reg rd_data_valid_stb_d3;
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| Line 233... |
Line 276... |
rd_addr_cache<=24'hFFFFFF;
|
rd_addr_cache<=24'hFFFFFF;
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rd_data_valid_stb_d1<=rd_data_valid_stb;
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rd_data_valid_stb_d1<=rd_data_valid_stb;
|
rd_data_valid_stb_d2<=rd_data_valid_stb_d1;
|
rd_data_valid_stb_d2<=rd_data_valid_stb_d1;
|
rd_data_valid_stb_d3<=rd_data_valid_stb_d2;
|
rd_data_valid_stb_d3<=rd_data_valid_stb_d2;
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rd_data_valid_stb_d4<=rd_data_valid_stb_d3;
|
rd_data_valid_stb_d4<=rd_data_valid_stb_d3;
|
|
fifo_full_d<=fifo_full;
|
|
if(wb_ack_o)
|
|
written<=0;
|
|
else
|
|
if(!fifo_full && fifo_full_d)
|
|
written<=1;
|
end
|
end
|
|
|
assign wb_ack_o=wb_we_i ? (wb_cyc_i && wb_stb_i && !fifo_full):rd_data_valid_stb_d2 && !rd_data_valid_stb_d3 || (!wb_we_i && rd_addr_cache==wb_adr_i[28:5]);
|
assign wb_ack_o=wb_we_i ? (wb_cyc_i && wb_stb_i && !fifo_full):(rd_data_valid_stb_d2 && !rd_data_valid_stb_d3) || (rd_addr_cache==wb_adr_i[28:5]);
|
|
|
always @(posedge ddr_clk)
|
always @(posedge ddr_clk)
|
begin
|
begin
|
wb_ack_d<=wb_ack_o;
|
wb_ack_d<=wb_ack_o;
|
wb_ack_d1<=wb_ack_d;
|
wb_ack_d1<=wb_ack_d;
|
if(rd_data_valid)
|
if(rd_data_valid)
|
begin
|
|
rd_data_fifo_out_d<=rd_data_fifo_out;
|
rd_data_fifo_out_d<=rd_data_fifo_out;
|
rd_data_valid_stb<=1;
|
|
end
|
|
else
|
|
if(wb_ack_d1)
|
|
rd_data_valid_stb<=0;
|
|
end
|
end
|
|
|
endmodule
|
endmodule
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No newline at end of file
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No newline at end of file
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