| Line 30... |
Line 30... |
wire [3:0] rdy;
|
wire [3:0] rdy;
|
wire dquery0=(!cpu) && store && (!blockstore);
|
wire dquery0=(!cpu) && store && (!blockstore);
|
wire dquery1= cpu && store && (!blockstore);
|
wire dquery1= cpu && store && (!blockstore);
|
wire dalloc0=(!cpu) && cacheable && (!invalidate) && load && (!prefetch);
|
wire dalloc0=(!cpu) && cacheable && (!invalidate) && load && (!prefetch);
|
wire dalloc1= cpu && cacheable && (!invalidate) && load && (!prefetch);
|
wire dalloc1= cpu && cacheable && (!invalidate) && load && (!prefetch);
|
wire ddealloc0=((!cpu) && (ifill || cas || swap || strstore || (store && blockstore))) ||
|
wire ddealloc0=((!cpu) && ((ifill && (!prefetch) && (!invalidate)) || cas || swap || strstore || (store && blockstore))) ||
|
( cpu && ((load && cacheable) || ifill || store || cas || swap || strload || strstore));
|
( cpu && ((load && cacheable && (!prefetch) && (!invalidate)) || (ifill && (!prefetch) && (!invalidate)) || store || cas || swap || strload || strstore));
|
wire ddealloc1=( cpu && (ifill || cas || swap || strstore || (store && blockstore))) ||
|
wire ddealloc1=( cpu && ((ifill && (!prefetch) && (!invalidate)) || cas || swap || strstore || (store && blockstore))) ||
|
((!cpu) && ((load && cacheable) || ifill || store || cas || swap || strload || strstore));
|
((!cpu) && ((load && cacheable && (!prefetch) && (!invalidate)) || (ifill && (!prefetch) && (!invalidate)) || store || cas || swap || strload || strstore));
|
|
|
wire iquery0=0;
|
wire iquery0=0;
|
wire iquery1=0;
|
wire iquery1=0;
|
wire ialloc0=(!cpu) && cacheable && (!invalidate) && ifill;
|
wire ialloc0=(!cpu) && cacheable && (!invalidate) && ifill;
|
wire ialloc1= cpu && cacheable && (!invalidate) && ifill;
|
wire ialloc1= cpu && cacheable && (!invalidate) && ifill;
|
wire idealloc0=((!cpu) && ((load && cacheable && (!prefetch) && (!invalidate)) || store || cas || swap || strstore)) ||
|
wire idealloc0=((!cpu) && ((load && cacheable && (!prefetch) && (!invalidate)) || store || cas || swap || strstore)) ||
|
( cpu && ((load && cacheable && (!prefetch) && (!invalidate)) || ifill || store || cas || swap || strload || strstore));
|
( cpu && ((load && cacheable && (!prefetch) && (!invalidate)) || (ifill && (!prefetch) && (!invalidate)) || store || cas || swap || strload || strstore));
|
wire idealloc1=( cpu && ((load && cacheable && (!prefetch) && (!invalidate)) || store || cas || swap || strstore )) ||
|
wire idealloc1=( cpu && ((load && cacheable && (!prefetch) && (!invalidate)) || store || cas || swap || strstore )) ||
|
((!cpu) && ((load && cacheable && (!prefetch) && (!invalidate)) || ifill || store || cas || swap || strload || strstore));
|
((!cpu) && ((load && cacheable && (!prefetch) && (!invalidate)) || (ifill && (!prefetch) && (!invalidate)) || store || cas || swap || strload || strstore));
|
|
|
|
|
wire [2:0] cpu0_dhit0;
|
wire [2:0] cpu0_dhit0;
|
wire [2:0] cpu0_dhit1;
|
wire [2:0] cpu0_dhit1;
|
wire [2:0] cpu1_dhit0;
|
wire [2:0] cpu1_dhit0;
|
