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Line 170... |
assign inval_vect0[87:64]=0;
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assign inval_vect0[87:64]=0;
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assign inval_vect0[90:88]={wayval0,cpu0_dhit0[2] && (address_d[5:4]==2'b11)};
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assign inval_vect0[90:88]={wayval0,cpu0_dhit0[2] && (address_d[5:4]==2'b11)};
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assign inval_vect0[93:91]={wayval0,cpu1_dhit0[2] && (address_d[5:4]==2'b11)};
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assign inval_vect0[93:91]={wayval0,cpu1_dhit0[2] && (address_d[5:4]==2'b11)};
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assign inval_vect0[111:94]=0;
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assign inval_vect0[111:94]=0;
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assign inval_vect1[3:0]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b00)};
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/*assign inval_vect1[3:0]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b00)};
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assign inval_vect1[7:4]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b00)};
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assign inval_vect1[7:4]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b00)};
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assign inval_vect1[31:8]=0;
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assign inval_vect1[34:32]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b01)};
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assign inval_vect1[37:35]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b01)};
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assign inval_vect1[55:38]=0;
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assign inval_vect1[59:56]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b10)};
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assign inval_vect1[63:60]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b10)};
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assign inval_vect1[87:64]=0;
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assign inval_vect1[90:88]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b11)};
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assign inval_vect1[93:91]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b11)};
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assign inval_vect1[111:94]=0;*/
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assign inval_vect1[3:0]=0;
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assign inval_vect1[7:4]=0;
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assign inval_vect1[31:8]=0;
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assign inval_vect1[31:8]=0;
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assign inval_vect1[34:32]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b01)};
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assign inval_vect1[34:32]={wayval1,cpu0_dhit1[2] && (address_d[5]==0)};
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assign inval_vect1[37:35]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b01)};
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assign inval_vect1[37:35]={wayval1,cpu1_dhit1[2] && (address_d[5]==0)};
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assign inval_vect1[55:38]=0;
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assign inval_vect1[55:38]=0;
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assign inval_vect1[59:56]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b10)};
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assign inval_vect1[59:56]=0;
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assign inval_vect1[63:60]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b10)};
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assign inval_vect1[63:60]=0;
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assign inval_vect1[87:64]=0;
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assign inval_vect1[87:64]=0;
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assign inval_vect1[90:88]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b11)};
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assign inval_vect1[90:88]={wayval1,cpu0_dhit1[2] && (address_d[5]==1)};
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assign inval_vect1[93:91]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b11)};
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assign inval_vect1[93:91]={wayval1,cpu1_dhit1[2] && (address_d[5]==1)};
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assign inval_vect1[111:94]=0;
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assign inval_vect1[111:94]=0;
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assign wayval0=cpu0_dhit0[1:0] | cpu1_dhit0[1:0] | cpu0_ihit[1:0] | cpu1_ihit[1:0];
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assign wayval0=cpu0_dhit0[1:0] | cpu1_dhit0[1:0] | cpu0_ihit[1:0] | cpu1_ihit[1:0];
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assign wayval1=cpu0_dhit1[1:0] | cpu1_dhit1[1:0];
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assign wayval1=cpu0_dhit1[1:0] | cpu1_dhit1[1:0];
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assign othercachehit[0]=((!cpu_d) && ifill_d && cpu0_dhit0[2]) ||
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assign othercachehit[0]=((!cpu_d) && ifill_d && cpu0_dhit0[2]) ||
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