| Line 585... |
Line 585... |
wb_we<=0; // Load first, as CAS
|
wb_we<=0; // Load first, as CAS
|
wb_sel<=8'b11111111; // SWAP/LDSTUB loads are as cacheline
|
wb_sel<=8'b11111111; // SWAP/LDSTUB loads are as cacheline
|
end
|
end
|
5'b01001://INT
|
5'b01001://INT
|
if(pcx_packet_d[117]) // Flush
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if(pcx_packet_d[117]) // Flush
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cpx_packet_1<={9'h171,13'h0,pcx_packet_d[64+5:64+4],3'b0,pcx_packet_d[64+11:64+6],30'h0,pcx_packet_d[17:0],46'b0,pcx_packet_d[17:0]}; //FLUSH instruction answer
|
cpx_packet_1<={9'h171,pcx_packet_d[113:112],11'h0,pcx_packet_d[64+5:64+4],3'b0,pcx_packet_d[64+11:64+6],30'h0,pcx_packet_d[17:0],46'b0,pcx_packet_d[17:0]}; //FLUSH instruction answer
|
else // Tread-to-thread interrupt
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else // Tread-to-thread interrupt
|
cpx_packet_1<={9'h170,54'h0,pcx_packet_d[17:0],46'h0,pcx_packet_d[17:0]};
|
cpx_packet_1<={9'h170,pcx_packet_d[113:112],52'h0,pcx_packet_d[17:0],46'h0,pcx_packet_d[17:0]};
|
//5'b01010: FP1 - processed by separate state
|
//5'b01010: FP1 - processed by separate state
|
//5'b01011: FP2 - processed by separate state
|
//5'b01011: FP2 - processed by separate state
|
//5'b01101: FWDREQ - not implemented
|
//5'b01101: FWDREQ - not implemented
|
//5'b01110: FWDREPL - not implemented
|
//5'b01110: FWDREPL - not implemented
|
5'b10000://IFILL
|
5'b10000://IFILL
|
| Line 744... |
Line 744... |
end
|
end
|
5'b00001://Store
|
5'b00001://Store
|
begin
|
begin
|
cpx_packet_1[143:140]<=4'b0100; // Type
|
cpx_packet_1[143:140]<=4'b0100; // Type
|
cpx_packet_1[127:0]<={2'b0,pcx_packet_d[109]/*BIS*/,2'b0,pcx_packet_d[64+5:64+4],3'b0,pcx_packet_d[64+11:64+6],store_inv_vec};
|
cpx_packet_1[127:0]<={2'b0,pcx_packet_d[109]/*BIS*/,2'b0,pcx_packet_d[64+5:64+4],3'b0,pcx_packet_d[64+11:64+6],store_inv_vec};
|
if((pcx_packet_d[110:109]==2'b01) && (pcx_packet_d[64+5:64]==0) && !inval_vect0[3] && !inval_vect1[3]) // Block init store
|
// if((pcx_packet_d[110:109]==2'b01) && (pcx_packet_d[64+5:64]==0) && !inval_vect0[3] && !inval_vect1[3]) // Block init store
|
state<=`PCX_BIS;
|
// state<=`PCX_BIS;
|
else
|
// else
|
begin
|
// begin
|
wb_cycle<=0;
|
wb_cycle<=0;
|
state<=`CPX_READY_1;
|
state<=`CPX_READY_1;
|
end
|
// end
|
end
|
end
|
5'b00010://CAS
|
5'b00010://CAS
|
begin
|
begin
|
cpx_packet_1[143:140]<=4'b0000; // Load return for first packet
|
cpx_packet_1[143:140]<=4'b0000; // Load return for first packet
|
cpx_packet_2[143:140]<=4'b0100; // Store ACK for second packet
|
cpx_packet_2[143:140]<=4'b0100; // Store ACK for second packet
|
