| Line 575... |
Line 575... |
end
|
end
|
5'b01001://INT
|
5'b01001://INT
|
if(pcx_packet_d[117]) // Flush
|
if(pcx_packet_d[117]) // Flush
|
begin
|
begin
|
cpx_packet_1<={9'h171,pcx_packet_d[113:112],11'h0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],30'h0,pcx_packet_d[17:0],46'b0,pcx_packet_d[17:0]}; //FLUSH instruction answer
|
cpx_packet_1<={9'h171,pcx_packet_d[113:112],11'h0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],30'h0,pcx_packet_d[17:0],46'b0,pcx_packet_d[17:0]}; //FLUSH instruction answer
|
cpx_packet_2<={9'h171,pcx_packet_d[113:112],11'h0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],30'h0,pcx_packet_d[17:0],46'b0,pcx_packet_d[17:0]}; //FLUSH instruction answer
|
//cpx_packet_2<={9'h171,pcx_packet_d[113:112],11'h0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],30'h0,pcx_packet_d[17:0],46'b0,pcx_packet_d[17:0]}; //FLUSH instruction answer
|
cpx_two_packet<=1;
|
//cpx_two_packet<=1;
|
cpu2<=!cpu; // Flush should be sent to both cores
|
//cpu2<=!cpu; // Flush should be sent to both cores
|
end
|
end
|
else // Tread-to-thread interrupt
|
else // Tread-to-thread interrupt
|
begin
|
begin
|
cpx_packet_1<={9'h170,pcx_packet_d[113:112],52'h0,pcx_packet_d[17:0],46'h0,pcx_packet_d[17:0]};
|
cpx_packet_1<={9'h170,pcx_packet_d[113:112],52'h0,pcx_packet_d[17:0],46'h0,pcx_packet_d[17:0]};
|
cpu<=pcx_packet_d[10];
|
cpu<=pcx_packet_d[10];
|
| Line 748... |
Line 748... |
state<=`PCX_REQ_STEP2;
|
state<=`PCX_REQ_STEP2;
|
end
|
end
|
5'b00101://STRSTORE
|
5'b00101://STRSTORE
|
begin
|
begin
|
cpx_packet_1[143:140]<=4'b0110; // Type
|
cpx_packet_1[143:140]<=4'b0110; // Type
|
cpx_packet_1[127:0]<={5'b0,pcx_packet_d[64+5:64+4],3'b0,pcx_packet_d[64+11:64+6],inval_vect0};
|
cpx_packet_1[127:0]<={5'b0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],inval_vect0};
|
wb_cycle<=0;
|
wb_cycle<=0;
|
state<=`CPX_READY_1;
|
state<=`CPX_READY_1;
|
end
|
end
|
5'b00110://SWAP/LDSTUB
|
5'b00110://SWAP/LDSTUB
|
begin
|
begin
|
cpx_packet_1[143:140]<=4'b0000; // Load return for first packet
|
cpx_packet_1[143:140]<=4'b0000; // Load return for first packet
|
cpx_packet_2[143:140]<=4'b0100; // Store ACK for second packet
|
cpx_packet_2[143:140]<=4'b0100; // Store ACK for second packet
|
cpx_packet_2[127:0]<={5'b0,pcx_packet_d[64+5:64+4],3'b0,pcx_packet_d[64+11:64+6],inval_vect0};
|
cpx_packet_2[127:0]<={5'b0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],inval_vect0};
|
cpx_packet_1[127:0]<={wb_data_i,wb_data_i};
|
cpx_packet_1[127:0]<={wb_data_i,wb_data_i};
|
state<=`PCX_REQ_STEP2;
|
state<=`PCX_REQ_STEP2;
|
end
|
end
|
5'b10000://IFILL
|
5'b10000://IFILL
|
begin
|
begin
|
| Line 1052... |
Line 1052... |
end
|
end
|
else
|
else
|
if(cpu2 && othercpuhit[1])
|
if(cpu2 && othercpuhit[1])
|
begin
|
begin
|
cpx_ready<=1;
|
cpx_ready<=1;
|
cpx_packet<={1'b1,4'b0011,12'b0,5'b0,pcx_packet_d[64+5:64+4],3'b000,pcx_packet_d[64+11:64+6],inval_vect1};;
|
cpx_packet<={1'b1,4'b0011,12'b0,5'b0,pcx_packet_d[64+5],1'b1,3'b000,pcx_packet_d[64+11:64+6],inval_vect1};;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
cpx_ready<=0;
|
cpx_ready<=0;
|
cpx_packet<=145'b0;
|
cpx_packet<=145'b0;
|
| Line 1068... |
Line 1068... |
end
|
end
|
else
|
else
|
if(!cpu2 && othercpuhit[1])
|
if(!cpu2 && othercpuhit[1])
|
begin
|
begin
|
cpx1_ready<=1;
|
cpx1_ready<=1;
|
cpx1_packet<={1'b1,4'b0011,12'b0,5'b0,pcx_packet_d[64+5:64+4],3'b001,pcx_packet_d[64+11:64+6],inval_vect1};;
|
cpx1_packet<={1'b1,4'b0011,12'b0,5'b0,pcx_packet_d[64+5],1'b1,3'b001,pcx_packet_d[64+11:64+6],inval_vect1};;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
cpx1_ready<=0;
|
cpx1_ready<=0;
|
cpx1_packet<=145'b0;
|
cpx1_packet<=145'b0;
|
