URL https://opencores.org/ocsvn/spdif_interface/spdif_interface/trunk

Subversion Repositories spdif_interface

[/] [spdif_interface/] [tags/] [spdif_rel_1/] [rtl/] [vhdl/] [gen_control_reg.vhd] - Diff between revs 13 and 37

Rev 13	Rev 37
Line 43...	Line 43...
`----------------------------------------------------------------------`	`----------------------------------------------------------------------`
`--`	`--`
`-- CVS Revision History`	`-- CVS Revision History`
`--`	`--`
`-- $Log: not supported by cvs2svn $`	`-- $Log: not supported by cvs2svn $`
	`-- Revision 1.3 2004/06/06 15:42:19 gedra`
	`-- Cleaned up lint warnings.`
	`--`
`-- Revision 1.2 2004/06/04 15:55:07 gedra`	`-- Revision 1.2 2004/06/04 15:55:07 gedra`
`-- Cleaned up lint warnings.`	`-- Cleaned up lint warnings.`
`--`	`--`
`-- Revision 1.1 2004/06/03 17:47:17 gedra`	`-- Revision 1.1 2004/06/03 17:47:17 gedra`
`-- Generic control register. Used in both recevier and transmitter.`	`-- Generic control register. Used in both recevier and transmitter.`
`--`	`--`
`--`	`--`

`library IEEE;`	`library ieee;`
`use IEEE.std_logic_1164.all;`	`use ieee.std_logic_1164.all;`
`use IEEE.std_logic_arith.all;`

`entity gen_control_reg is`	`entity gen_control_reg is`
`generic (DATA_WIDTH: integer;`	`generic (DATA_WIDTH: integer;`
`-- note that this vector is (0 to xx), reverse order`	`-- note that this vector is (0 to xx), reverse order`
`ACTIVE_BIT_MASK: std_logic_vector);`	`ACTIVE_BIT_MASK: std_logic_vector);`