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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.1 2004/06/03 17:45:18 gedra
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-- SPDIF signal generator.
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--
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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entity spdif_source is
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entity spdif_source is
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generic (Freq: natural); -- Sampling frequency in Hz
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generic (FREQ: natural); -- Sampling frequency in Hz
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port ( -- Bitrate is 64x sampling frequency
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port ( -- Bitrate is 64x sampling frequency
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reset: in std_logic;
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reset: in std_logic;
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spdif: out std_logic); -- Output bi-phase encoded signal
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spdif: out std_logic); -- Output bi-phase encoded signal
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end spdif_source;
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end spdif_source;
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-- Generate SPDIF signal
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-- Generate SPDIF signal
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SGEN: process (clk, reset)
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SGEN: process (clk, reset)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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fcnt <= 189; -- start just before block to shorten simulation
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fcnt <= 188; -- start just before block to shorten simulation
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bcnt <= 0;
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bcnt <= 0;
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toggle <= 0;
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toggle <= 0;
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ispdif <= '0';
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ispdif <= '0';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if toggle = 1 then
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if toggle = 1 then
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end if;
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end if;
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end process SGEN;
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end process SGEN;
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-- Clock process, generate a clock based on the desired sampling frequency
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-- Clock process, generate a clock based on the desired sampling frequency
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CLKG: process
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CLKG: process
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variable t1: time := 1.0e12/real(freq*256) * 1 ps;
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variable t1: time := 1.0e12/real(FREQ*256) * 1 ps;
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begin
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begin
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clk <= '0';
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clk <= '0';
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wait for t1;
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wait for t1;
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clk <= '1';
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clk <= '1';
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wait for t1;
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wait for t1;
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