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----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2004/06/06 15:45:24 gedra
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-- Cleaned up lint warnings.
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--
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-- Revision 1.1 2004/06/03 17:45:18 gedra
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-- Revision 1.1 2004/06/03 17:45:18 gedra
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-- SPDIF signal generator.
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-- SPDIF signal generator.
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--
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--
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--
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--
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LIBRARY ieee;
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library ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.std_logic_1164.all;
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entity spdif_source is
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entity spdif_source is
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generic (FREQ: natural); -- Sampling frequency in Hz
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generic (FREQ: natural); -- Sampling frequency in Hz
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port ( -- Bitrate is 64x sampling frequency
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port ( -- Bitrate is 64x sampling frequency
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reset: in std_logic;
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reset: in std_logic;
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constant X_Preamble : std_logic_vector(7 downto 0) := "11100010";
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constant X_Preamble : std_logic_vector(7 downto 0) := "11100010";
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constant Y_Preamble : std_logic_vector(7 downto 0) := "11100100";
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constant Y_Preamble : std_logic_vector(7 downto 0) := "11100100";
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constant Z_Preamble : std_logic_vector(7 downto 0) := "11101000";
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constant Z_Preamble : std_logic_vector(7 downto 0) := "11101000";
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signal clk, ispdif: std_logic;
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signal clk, ispdif: std_logic;
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signal fcnt : integer; -- frame counter
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signal fcnt : natural range 0 to 191; -- frame counter
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signal bcnt : integer; -- subframe bit counter
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signal bcnt : natural range 0 to 63; -- subframe bit counter
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signal pcnt : integer;
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signal pcnt : natural range 0 to 63; -- parity counter
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signal toggle : integer range 0 to 1;
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signal toggle : integer range 0 to 1;
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-- Channel A: sinewave with frequency=Freq/12
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-- Channel A: sinewave with frequency=Freq/12
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type sine16 is array (0 to 15) of std_logic_vector(15 downto 0);
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type sine16 is array (0 to 15) of std_logic_vector(15 downto 0);
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signal channel_a : sine16 := ((x"8000"),(x"b0fb"),(x"da82"),(x"f641"),
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signal channel_a : sine16 := ((x"8000"),(x"b0fb"),(x"da82"),(x"f641"),
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(x"ffff"), (x"f641"), (x"da82"), (x"b0fb"),
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(x"ffff"), (x"f641"), (x"da82"), (x"b0fb"),
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-- Generate SPDIF signal
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-- Generate SPDIF signal
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SGEN: process (clk, reset)
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SGEN: process (clk, reset)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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fcnt <= 188; -- start just before block to shorten simulation
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fcnt <= 184; -- start just before block to shorten simulation
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bcnt <= 0;
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bcnt <= 0;
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toggle <= 0;
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toggle <= 0;
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ispdif <= '0';
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ispdif <= '0';
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pcnt <= 0;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if toggle = 1 then
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if toggle = 1 then
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-- frame counter: 0 to 191
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-- frame counter: 0 to 191
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if fcnt < 191 then
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if fcnt < 191 then
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if bcnt = 63 then
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if bcnt = 63 then
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