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[/] [spdif_interface/] [trunk/] [rtl/] [vhdl/] [dpram_altera.vhd] - Diff between revs 27 and 28

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Rev 27	Rev 28
Line 44...	Line 44...
`----------------------------------------------------------------------`	`----------------------------------------------------------------------`
`--`	`--`
`-- CVS Revision History`	`-- CVS Revision History`
`--`	`--`
`-- $Log: not supported by cvs2svn $`	`-- $Log: not supported by cvs2svn $`
	`-- Revision 1.1 2004/06/18 18:40:04 gedra`
	`-- Alternate dual port memory implementation for Altera FPGA's.`
	`--`
`--`	`--`

`library ieee;`	`library ieee;`
`use ieee.std_logic_1164.all;`	`use ieee.std_logic_1164.all;`
`use ieee.std_logic_unsigned.all;`	`--use ieee.std_logic_unsigned.all;`
	`library lpm;`
	`use lpm.lpm_components.all;`

`entity dpram is`	`entity dpram is`
`generic (DATA_WIDTH: positive;`	`generic (DATA_WIDTH: positive;`
`RAM_WIDTH: positive);`	`RAM_WIDTH: positive);`
`port (`	`port (`
Line 64...	Line 69...
`wr_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0);`	`wr_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0);`
`rd_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0);`	`rd_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0);`
`dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));`	`dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));`
`end dpram;`	`end dpram;`

`--library lpm;`	`architecture altera of dpram is`
`--USE lpm.lpm_components.all;`
`architecture rtl of dpram is`

`component lpm_ram_dp`	`component lpm_ram_dp`
`generic ( LPM_WIDTH: positive;`	`generic ( LPM_WIDTH: positive;`
`LPM_WIDTHAD: positive;`	`LPM_WIDTHAD: positive;`
`LPM_NUMWORDS: natural := 0;`	`LPM_NUMWORDS: natural := 0;`
Line 93...	Line 96...

`begin`	`begin`

`one <= '1';`	`one <= '1';`

`RAM: lpm_ram_dp`	`ram: lpm_ram_dp`
`generic map(LPM_WIDTH => DATA_WIDTH,`	`generic map(LPM_WIDTH => DATA_WIDTH,`
`LPM_WIDTHAD => RAM_WIDTH,`	`LPM_WIDTHAD => RAM_WIDTH,`
`LPM_NUMWORDS => 2**(RAM_WIDTH - 1))`	`LPM_NUMWORDS => 2**(RAM_WIDTH - 1))`
`port map (data => din,`	`port map (data => din,`
`rdaddress => rd_addr,`	`rdaddress => rd_addr,`
Line 108...	Line 111...
`rdclken => one,`	`rdclken => one,`
`wrclken => one,`	`wrclken => one,`
`wren => wr_en,`	`wren => wr_en,`
`q => dout);`	`q => dout);`

`end rtl;`	`end altera;`

`No newline at end of file`	`No newline at end of file`

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[/] [spdif_interface/] [trunk/] [rtl/] [vhdl/] [dpram_altera.vhd] - Diff between revs 27 and 28