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----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2004/06/04 15:55:07 gedra
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-- Cleaned up lint warnings.
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--
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-- Revision 1.1 2004/06/03 17:47:17 gedra
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-- Revision 1.1 2004/06/03 17:47:17 gedra
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-- Generic control register. Used in both recevier and transmitter.
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-- Generic control register. Used in both recevier and transmitter.
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--
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--
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--
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--
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| Line 54... |
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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entity gen_control_reg is
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entity gen_control_reg is
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generic (DATA_WIDTH: integer;
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generic (DATA_WIDTH: integer;
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ACTIVE_BIT_MASK: std_logic_vector); -- note that this vector is (0 to xx),
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-- note that this vector is (0 to xx), reverse order
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port ( -- reverse order
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ACTIVE_BIT_MASK: std_logic_vector);
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port (
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clk: in std_logic; -- clock
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clk: in std_logic; -- clock
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rst: in std_logic; -- reset
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rst: in std_logic; -- reset
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ctrl_wr: in std_logic; -- control register write
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ctrl_wr: in std_logic; -- control register write
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ctrl_rd: in std_logic; -- control register read
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ctrl_rd: in std_logic; -- control register read
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ctrl_din: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data
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ctrl_din: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data
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