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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.1 2004/06/03 17:47:17 gedra
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-- Generic control register. Used in both recevier and transmitter.
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--
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--
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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entity gen_control_reg is
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entity gen_control_reg is
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generic (DataWidth: integer;
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generic (DATA_WIDTH: integer;
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ActiveBitsMask: std_logic_vector); -- note that this vector is (0 to xx), reverse order
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ACTIVE_BIT_MASK: std_logic_vector); -- note that this vector is (0 to xx),
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port (
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port ( -- reverse order
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clk: in std_logic; -- clock
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clk: in std_logic; -- clock
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rst: in std_logic; -- reset
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rst: in std_logic; -- reset
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ctrl_wr: in std_logic; -- control register write
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ctrl_wr: in std_logic; -- control register write
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ctrl_rd: in std_logic; -- control register read
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ctrl_rd: in std_logic; -- control register read
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ctrl_din: in std_logic_vector(DataWidth - 1 downto 0); -- write data
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ctrl_din: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data
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ctrl_dout: out std_logic_vector(DataWidth - 1 downto 0); -- read data
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ctrl_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data
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ctrl_bits: out std_logic_vector(DataWidth - 1 downto 0)); -- control bits
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ctrl_bits: out std_logic_vector(DATA_WIDTH - 1 downto 0)); -- control bits
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end gen_control_reg;
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end gen_control_reg;
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architecture rtl of gen_control_reg is
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architecture rtl of gen_control_reg is
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signal ctrl_internal, BitMask: std_logic_vector(DataWidth - 1 downto 0);
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signal ctrl_internal: std_logic_vector(DATA_WIDTH - 1 downto 0);
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begin
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begin
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ctrl_dout <= ctrl_internal when ctrl_rd = '1' else (others => '0');
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ctrl_dout <= ctrl_internal when ctrl_rd = '1' else (others => '0');
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ctrl_bits <= ctrl_internal;
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ctrl_bits <= ctrl_internal;
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-- control register generation
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-- control register generation
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--BitMask <= CONV_STD_LOGIC_VECTOR(ActiveBitsMask, ctrl_din'length);
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CTRLREG: for k in ctrl_din'range generate
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CTRLREG: for k in ctrl_din'range generate
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ACTIVE: if ActiveBitsMask(k) = '1' generate -- active bits can be written to
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-- active bits can be written to
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ACTIVE: if ACTIVE_BIT_MASK(k) = '1' generate
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CBIT: process (clk, rst)
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CBIT: process (clk, rst)
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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ctrl_internal(k) <= '0';
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ctrl_internal(k) <= '0';
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else
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else
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ctrl_internal(k) <= ctrl_din(k);
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ctrl_internal(k) <= ctrl_din(k);
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process CBIT;
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end process CBIT;
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end generate;
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end generate ACTIVE;
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INACTIVE: if ActiveBitsMask(k) = '0' generate -- inactive bits are always 0
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-- inactive bits are always 0
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INACTIVE: if ACTIVE_BIT_MASK(k) = '0' generate
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ctrl_internal(k) <= '0';
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ctrl_internal(k) <= '0';
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end generate;
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end generate INACTIVE;
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end generate;
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end generate CTRLREG;
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end rtl;
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end rtl;
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