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https://opencores.org/ocsvn/spdif_interface/spdif_interface/trunk
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.3 2004/06/06 15:42:20 gedra
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-- Cleaned up lint warnings.
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--
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-- Revision 1.2 2004/06/04 15:55:07 gedra
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-- Revision 1.2 2004/06/04 15:55:07 gedra
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-- Cleaned up lint warnings.
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-- Cleaned up lint warnings.
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--
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--
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-- Revision 1.1 2004/06/03 17:49:26 gedra
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-- Revision 1.1 2004/06/03 17:49:26 gedra
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-- Generic event register. Used in both receiver and transmitter.
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-- Generic event register. Used in both receiver and transmitter.
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end gen_event_reg;
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end gen_event_reg;
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architecture rtl of gen_event_reg is
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architecture rtl of gen_event_reg is
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signal evt_internal, zero: std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal evt_internal, zero: std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal zevent: std_logic_vector(DATA_WIDTH - 1 downto 0);
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begin
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begin
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evt_dout <= evt_internal when evt_rd = '1' else (others => '0');
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evt_dout <= evt_internal when evt_rd = '1' else (others => '0');
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zero <= (others => '0');
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zero <= (others => '0');
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EVTREG: for k in evt_din'range generate
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EVTREG: for k in evt_din'range generate
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EBIT: process (clk, rst)
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EBIT: process (clk, rst)
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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evt_internal(k) <= '0';
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evt_internal(k) <= '0';
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zevent(k) <= event(k);
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else
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else
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if rising_edge(clk) then
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if rising_edge(clk) then
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if event(k) = '1' then -- set event
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zevent(k) <= event(k);
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if event(k) /= zevent(k) then -- set event
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evt_internal(k) <= '1';
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evt_internal(k) <= '1';
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elsif evt_wr = '1' and evt_din(k) = '1' then -- clear event
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elsif evt_wr = '1' and evt_din(k) = '1' then -- clear event
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evt_internal(k) <= '0';
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evt_internal(k) <= '0';
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end if;
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end if;
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end if;
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end if;
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