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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.1 2004/06/03 17:49:26 gedra
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-- Generic event register. Used in both receiver and transmitter.
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--
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--
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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entity gen_event_reg is
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entity gen_event_reg is
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generic (DataWidth: integer:=32);
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generic (DATA_WIDTH: integer:=32);
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port (
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port (
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clk: in std_logic; -- clock
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clk: in std_logic; -- clock
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rst: in std_logic; -- reset
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rst: in std_logic; -- reset
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evt_wr: in std_logic; -- event register write
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evt_wr: in std_logic; -- event register write
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evt_rd: in std_logic; -- event register read
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evt_rd: in std_logic; -- event register read
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evt_din: in std_logic_vector(DataWidth - 1 downto 0); -- write data
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evt_din: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data
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evt_dout: out std_logic_vector(DataWidth - 1 downto 0); -- read data
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event: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- event vector
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event: in std_logic_vector(DataWidth - 1 downto 0); -- event vector
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evt_mask: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- irq mask
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evt_mask: in std_logic_vector(DataWidth - 1 downto 0); -- irq mask
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evt_en: in std_logic; -- irq enable
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evt_en: in std_logic; -- irq enable
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evt_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data
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evt_irq: out std_logic); -- interrupt request
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evt_irq: out std_logic); -- interrupt request
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end gen_event_reg;
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end gen_event_reg;
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architecture rtl of gen_event_reg is
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architecture rtl of gen_event_reg is
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signal evt_internal, zero: std_logic_vector(DataWidth - 1 downto 0);
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signal evt_internal, zero: std_logic_vector(DATA_WIDTH - 1 downto 0);
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begin
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begin
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evt_dout <= evt_internal when evt_rd = '1' else (others => '0');
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evt_dout <= evt_internal when evt_rd = '1' else (others => '0');
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zero <= (others => '0');
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zero <= (others => '0');
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-- IRQ generation:
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-- IRQ generation:
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-- IRQ signal will pulse low when writing to the event register. This will capture situations
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-- IRQ signal will pulse low when writing to the event register. This will
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-- when not all active events are cleared or an event happens at the same time as it is cleared.
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-- capture situations when not all active events are cleared or an event happens
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-- at the same time as it is cleared.
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IR: process (clk)
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IR: process (clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if ((evt_internal and evt_mask) /= zero) and evt_wr = '0' and evt_en = '1' then
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if ((evt_internal and evt_mask) /= zero) and evt_wr = '0' and evt_en = '1' then
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evt_irq <= '1';
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evt_irq <= '1';
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evt_internal(k) <= '0';
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evt_internal(k) <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process EBIT;
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end process EBIT;
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end generate;
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end generate EVTREG;
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end rtl;
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end rtl;
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