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----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.1 2004/06/05 17:16:46 gedra
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-- Channel status/user data capture register
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--
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--
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--
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library IEEE;
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library ieee;
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use IEEE.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use work.rx_package.all;
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use work.rx_package.all;
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entity rx_cap_reg is
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entity rx_cap_reg is
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port (
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port (
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clk: in std_logic; -- clock
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clk: in std_logic; -- clock
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Line 99... |
ctrl_rd => cap_ctrl_rd,
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ctrl_rd => cap_ctrl_rd,
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ctrl_din => cap_din,
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ctrl_din => cap_din,
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ctrl_dout => cap_ctrl_dout,
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ctrl_dout => cap_ctrl_dout,
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ctrl_bits => cap_ctrl_bits);
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ctrl_bits => cap_ctrl_bits);
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bitlen <= CONV_INTEGER(cap_ctrl_bits(5 downto 0));
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bitlen <= to_integer(unsigned(cap_ctrl_bits(5 downto 0)));
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chid <= cap_ctrl_bits(6);
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chid <= cap_ctrl_bits(6);
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cdata <= cap_ctrl_bits(7);
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cdata <= cap_ctrl_bits(7);
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bitpos <= CONV_INTEGER(cap_ctrl_bits(15 downto 8));
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bitpos <= to_integer(unsigned(cap_ctrl_bits(15 downto 8)));
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-- capture data register
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-- capture data register
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CDAT: process (clk, rst)
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CDAT: process (clk, rst)
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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Line 159... |
end if;
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end if;
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-- if all bits captured, check with previous data
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-- if all bits captured, check with previous data
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if cap_len = bitlen and compared = '0' then
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if cap_len = bitlen and compared = '0' then
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compared <= '1';
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compared <= '1';
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-- event generated if captured bits differ
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-- event generated if captured bits differ
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if CONV_INTEGER(cap_reg) /= CONV_INTEGER(cap_new) then
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if cap_reg /= cap_new then
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cap_evt <= '1';
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cap_evt <= '1';
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end if;
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end if;
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cap_reg <= cap_new;
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cap_reg <= cap_new;
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else
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else
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cap_evt <= '0';
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cap_evt <= '0';
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