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----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2004/06/16 19:04:09 gedra
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-- Fixed a few bugs.
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--
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-- Revision 1.1 2004/06/13 18:07:47 gedra
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-- Revision 1.1 2004/06/13 18:07:47 gedra
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-- Frame decoder and sample extractor
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-- Frame decoder and sample extractor
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--
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--
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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entity rx_decode is
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entity rx_decode is
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generic (DATA_WIDTH: integer range 16 to 32;
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generic (DATA_WIDTH: integer range 16 to 32;
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ADDR_WIDTH: integer range 8 to 64);
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ADDR_WIDTH: integer range 8 to 64);
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port (
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port (
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signal adr_cnt : integer range 0 to 2**(ADDR_WIDTH - 1) - 1;
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signal adr_cnt : integer range 0 to 2**(ADDR_WIDTH - 1) - 1;
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type samp_states is (IDLE, CHA_SYNC, GET_SAMP, PAR_CHK);
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type samp_states is (IDLE, CHA_SYNC, GET_SAMP, PAR_CHK);
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signal sampst : samp_states;
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signal sampst : samp_states;
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signal bit_cnt, par_cnt : integer range 0 to 31;
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signal bit_cnt, par_cnt : integer range 0 to 31;
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signal samp_start : integer range 0 to 15;
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signal samp_start : integer range 0 to 15;
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signal tmp_data : std_logic_vector(DATA_WIDTH - 6 downto 0);
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signal tmp_data : std_logic_vector(26 downto 0);
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signal tmp_stat : std_logic_vector(4 downto 0);
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signal tmp_stat : std_logic_vector(4 downto 0);
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signal valid, next_is_a, blk_start : std_logic;
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signal valid, next_is_a, blk_start : std_logic;
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begin
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begin
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next_is_a <= '1';
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next_is_a <= '1';
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if lock = '1' and conf_sample = '1' then
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if lock = '1' and conf_sample = '1' then
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sampst <= CHA_SYNC;
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sampst <= CHA_SYNC;
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end if;
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end if;
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when CHA_SYNC =>
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when CHA_SYNC =>
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wr_addr <= CONV_STD_LOGIC_VECTOR(adr_cnt, ADDR_WIDTH - 1);
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wr_addr <= std_logic_vector(to_unsigned(adr_cnt, ADDR_WIDTH - 1));
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wr_en <= '0';
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wr_en <= '0';
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bit_cnt <= 0;
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bit_cnt <= 0;
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valid <= '0';
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valid <= '0';
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par_cnt <= 0;
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par_cnt <= 0;
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stat_paritya <= '0';
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stat_paritya <= '0';
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stat_parityb <= '0';
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stat_parityb <= '0';
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stat_lsbf <= '0';
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stat_lsbf <= '0';
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stat_hsbf <= '0';
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stat_hsbf <= '0';
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tmp_data(DATA_WIDTH - 6 downto 0) <= (others => '0');
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tmp_data(26 downto 0) <= (others => '0');
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if rx_block_start = '1' and conf_blken = '1' then
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if rx_block_start = '1' and conf_blken = '1' then
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blk_start <= '1';
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blk_start <= '1';
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end if;
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end if;
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if rx_frame_start = '1' and rx_channel_a = next_is_a then
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if rx_frame_start = '1' and rx_channel_a = next_is_a then
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next_is_a <= not next_is_a;
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next_is_a <= not next_is_a;
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