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https://opencores.org/ocsvn/spdif_interface/spdif_interface/trunk
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2004/06/09 19:24:50 gedra
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-- Added dual port ram.
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--
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-- Revision 1.1 2004/06/07 18:06:00 gedra
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-- Revision 1.1 2004/06/07 18:06:00 gedra
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-- Receiver component declarations.
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-- Receiver component declarations.
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--
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--
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--
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--
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cs_b_en: out std_logic); -- channel status ch. B enable);
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cs_b_en: out std_logic); -- channel status ch. B enable);
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end component;
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end component;
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component dpram
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component dpram
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generic (DATA_WIDTH: positive;
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generic (DATA_WIDTH: positive;
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ADDR_WIDTH: positive);
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RAM_WIDTH: positive);
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port (
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port (
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clk: in std_logic;
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clk: in std_logic;
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rst: in std_logic; -- reset is optional, not used here
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rst: in std_logic; -- reset is optional, not used here
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din: in std_logic_vector(DATA_WIDTH - 1 downto 0);
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din: in std_logic_vector(DATA_WIDTH - 1 downto 0);
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wr_en: in std_logic;
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wr_en: in std_logic;
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rd_en: in std_logic;
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rd_en: in std_logic;
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wr_addr: in std_logic_vector(ADDR_WIDTH - 1 downto 0);
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wr_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0);
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rd_addr: in std_logic_vector(ADDR_WIDTH - 1 downto 0);
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rd_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0);
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dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));
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dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));
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end component;
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end component;
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end rx_package;
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end rx_package;
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