| Line 43... |
Line 43... |
----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.3 2004/06/10 18:57:36 gedra
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-- Cleaned up lint warnings.
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--
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-- Revision 1.2 2004/06/09 19:24:50 gedra
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-- Revision 1.2 2004/06/09 19:24:50 gedra
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-- Added dual port ram.
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-- Added dual port ram.
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--
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--
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-- Revision 1.1 2004/06/07 18:06:00 gedra
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-- Revision 1.1 2004/06/07 18:06:00 gedra
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-- Receiver component declarations.
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-- Receiver component declarations.
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| Line 125... |
Line 128... |
cap_dout: out std_logic_vector(31 downto 0); -- read data
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cap_dout: out std_logic_vector(31 downto 0); -- read data
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cap_evt: out std_logic); -- capture event (interrupt)
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cap_evt: out std_logic); -- capture event (interrupt)
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end component;
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end component;
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component rx_phase_det
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component rx_phase_det
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generic (WISH_BONE_FREQ: natural := 33); -- WishBone frequency in MHz
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generic (WISHBONE_FREQ: natural := 33); -- WishBone frequency in MHz
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port (
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port (
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wb_clk_i: in std_logic;
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wb_clk_i: in std_logic;
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rxen: in std_logic;
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rxen: in std_logic;
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spdif: in std_logic;
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spdif: in std_logic;
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lock: out std_logic;
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lock: out std_logic;
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| Line 157... |
Line 160... |
wr_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0);
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wr_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0);
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rd_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0);
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rd_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0);
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dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));
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dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));
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end component;
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end component;
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component rx_decode
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generic (DATA_WIDTH: integer range 16 to 32;
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ADDR_WIDTH: integer range 8 to 64);
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port (
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wb_clk_i: in std_logic;
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conf_rxen: in std_logic;
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conf_sample: in std_logic;
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conf_valid: in std_logic;
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conf_mode: in std_logic_vector(3 downto 0);
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conf_blken: in std_logic;
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conf_valen: in std_logic;
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conf_useren: in std_logic;
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conf_staten: in std_logic;
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conf_paren: in std_logic;
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lock: in std_logic;
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rx_data: in std_logic;
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rx_data_en: in std_logic;
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rx_block_start: in std_logic;
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rx_frame_start: in std_logic;
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rx_channel_a: in std_logic;
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wr_en: out std_logic;
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wr_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0);
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wr_data: out std_logic_vector(DATA_WIDTH downto 0);
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stat_paritya: out std_logic;
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stat_parityb: out std_logic;
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stat_lsbf: out std_logic;
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stat_hsbf: out std_logic);
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end component;
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end rx_package;
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end rx_package;
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No newline at end of file
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No newline at end of file
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