Line 43... |
Line 43... |
----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.6 2004/06/23 18:10:17 gedra
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-- Added Wishbone bus cycle decoder.
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--
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-- Revision 1.5 2004/06/16 19:03:45 gedra
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-- Revision 1.5 2004/06/16 19:03:45 gedra
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-- Changed status reg. declaration
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-- Changed status reg. declaration
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--
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--
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-- Revision 1.4 2004/06/13 18:08:09 gedra
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-- Revision 1.4 2004/06/13 18:08:09 gedra
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-- Added frame decoder and sample extractor
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-- Added frame decoder and sample extractor
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Line 194... |
Line 197... |
rx_block_start: in std_logic;
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rx_block_start: in std_logic;
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rx_frame_start: in std_logic;
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rx_frame_start: in std_logic;
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rx_channel_a: in std_logic;
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rx_channel_a: in std_logic;
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wr_en: out std_logic;
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wr_en: out std_logic;
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wr_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0);
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wr_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0);
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wr_data: out std_logic_vector(DATA_WIDTH downto 0);
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wr_data: out std_logic_vector(DATA_WIDTH - 1 downto 0);
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stat_paritya: out std_logic;
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stat_paritya: out std_logic;
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stat_parityb: out std_logic;
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stat_parityb: out std_logic;
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stat_lsbf: out std_logic;
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stat_lsbf: out std_logic;
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stat_hsbf: out std_logic);
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stat_hsbf: out std_logic);
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end component;
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end component;
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