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[/] [spdif_interface/] [trunk/] [rtl/] [vhdl/] [rx_package.vhd] - Diff between revs 30 and 37

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Rev 30 Rev 37
Line 43... Line 43...
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--
--
-- CVS Revision History
-- CVS Revision History
--
--
-- $Log: not supported by cvs2svn $
-- $Log: not supported by cvs2svn $
 
-- Revision 1.6  2004/06/23 18:10:17  gedra
 
-- Added Wishbone bus cycle decoder.
 
--
-- Revision 1.5  2004/06/16 19:03:45  gedra
-- Revision 1.5  2004/06/16 19:03:45  gedra
-- Changed status reg. declaration
-- Changed status reg. declaration
--
--
-- Revision 1.4  2004/06/13 18:08:09  gedra
-- Revision 1.4  2004/06/13 18:08:09  gedra
-- Added frame decoder and sample extractor
-- Added frame decoder and sample extractor
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      rx_block_start: in std_logic;
      rx_block_start: in std_logic;
      rx_frame_start: in std_logic;
      rx_frame_start: in std_logic;
      rx_channel_a: in std_logic;
      rx_channel_a: in std_logic;
      wr_en: out std_logic;
      wr_en: out std_logic;
      wr_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0);
      wr_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0);
      wr_data: out std_logic_vector(DATA_WIDTH downto 0);
      wr_data: out std_logic_vector(DATA_WIDTH - 1 downto 0);
      stat_paritya: out std_logic;
      stat_paritya: out std_logic;
      stat_parityb: out std_logic;
      stat_parityb: out std_logic;
      stat_lsbf: out std_logic;
      stat_lsbf: out std_logic;
      stat_hsbf: out std_logic);
      stat_hsbf: out std_logic);
  end component;
  end component;

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