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Line 43... |
----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.7 2004/06/26 14:14:47 gedra
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-- Converted to numeric_std and fixed a few bugs.
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--
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-- Revision 1.6 2004/06/23 18:10:17 gedra
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-- Revision 1.6 2004/06/23 18:10:17 gedra
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-- Added Wishbone bus cycle decoder.
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-- Added Wishbone bus cycle decoder.
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--
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--
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-- Revision 1.5 2004/06/16 19:03:45 gedra
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-- Revision 1.5 2004/06/16 19:03:45 gedra
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-- Changed status reg. declaration
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-- Changed status reg. declaration
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| Line 102... |
Line 105... |
port (
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port (
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wb_clk_i: in std_logic; -- clock
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wb_clk_i: in std_logic; -- clock
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status_rd: in std_logic; -- status register read
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status_rd: in std_logic; -- status register read
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lock: in std_logic; -- signal lock status
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lock: in std_logic; -- signal lock status
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chas: in std_logic; -- channel A or B select
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chas: in std_logic; -- channel A or B select
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rx_frame_start: in std_logic; -- start of frame signal
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rx_block_start: in std_logic; -- start of block signal
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ch_data: in std_logic; -- channel status/user data
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ch_data: in std_logic; -- channel status/user data
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cs_a_en: in std_logic; -- channel status ch. A enable
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cs_a_en: in std_logic; -- channel status ch. A enable
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cs_b_en: in std_logic; -- channel status ch. B enable
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cs_b_en: in std_logic; -- channel status ch. B enable
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status_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));
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status_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));
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end component;
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end component;
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| Line 132... |
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rst: in std_logic; -- reset
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rst: in std_logic; -- reset
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cap_ctrl_wr: in std_logic; -- control register write
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cap_ctrl_wr: in std_logic; -- control register write
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cap_ctrl_rd: in std_logic; -- control register read
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cap_ctrl_rd: in std_logic; -- control register read
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cap_data_rd: in std_logic; -- data register read
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cap_data_rd: in std_logic; -- data register read
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cap_din: in std_logic_vector(31 downto 0); -- write data
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cap_din: in std_logic_vector(31 downto 0); -- write data
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frame_rst: in std_logic; -- start of frame signal
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rx_block_start: in std_logic; -- start of block signal
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ch_data: in std_logic; -- channel status/user data
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ch_data: in std_logic; -- channel status/user data
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ud_a_en: in std_logic; -- user data ch. A enable
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ud_a_en: in std_logic; -- user data ch. A enable
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ud_b_en: in std_logic; -- user data ch. B enable
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ud_b_en: in std_logic; -- user data ch. B enable
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cs_a_en: in std_logic; -- channel status ch. A enable
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cs_a_en: in std_logic; -- channel status ch. A enable
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cs_b_en: in std_logic; -- channel status ch. B enable
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cs_b_en: in std_logic; -- channel status ch. B enable
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