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----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.1 2004/06/06 15:43:02 gedra
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-- Early version of the bi-phase mark decoder.
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--
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--
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--
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LIBRARY ieee;
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library ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.std_logic_1164.all;
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entity rx_phase_det is
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entity rx_phase_det is
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generic (WISH_BONE_FREQ: natural := 33); -- WishBone frequency in MHz
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generic (WISHBONE_FREQ: natural := 33); -- WishBone frequency in MHz
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port (
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port (
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wb_clk_i: in std_logic;
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wb_clk_i: in std_logic; -- wishbone clock
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rxen: in std_logic;
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rxen: in std_logic; -- phase detector enable
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spdif: in std_logic;
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spdif: in std_logic; -- SPDIF input signal
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lock: out std_logic;
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lock: out std_logic; -- true if locked to spdif input
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rx_data: out std_logic;
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rx_data: out std_logic; -- recevied data
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rx_data_en: out std_logic;
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rx_data_en: out std_logic; -- received data enable
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rx_block_start: out std_logic;
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rx_block_start: out std_logic; -- start-of-block pulse
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rx_frame_start: out std_logic;
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rx_frame_start: out std_logic; -- start-of-frame pulse
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rx_channel_a: out std_logic;
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rx_channel_a: out std_logic; -- 1 if channel A frame is recevied
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rx_error: out std_logic;
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rx_error: out std_logic; -- signal error was detected
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ud_a_en: out std_logic; -- user data ch. A enable
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ud_a_en: out std_logic; -- user data ch. A enable
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ud_b_en: out std_logic; -- user data ch. B enable
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ud_b_en: out std_logic; -- user data ch. B enable
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cs_a_en: out std_logic; -- channel status ch. A enable
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cs_a_en: out std_logic; -- channel status ch. A enable
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cs_b_en: out std_logic); -- channel status ch. B enable);
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cs_b_en: out std_logic); -- channel status ch. B enable);
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end rx_phase_det;
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end rx_phase_det;
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architecture rtl of rx_phase_det is
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architecture rtl of rx_phase_det is
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constant TRANSITIONS : integer := 40;
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constant TRANSITIONS : integer := 40;
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constant FRAMES_FOR_LOCK : integer := 3;
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constant FRAMES_FOR_LOCK : integer := 3;
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signal maxpulse, maxp, mp_cnt: integer range 0 to 16 * WISH_BONE_FREQ;
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signal maxpulse, maxp, mp_cnt: integer range 0 to 16 * WISHBONE_FREQ;
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signal last_cnt, max_thres : integer range 0 to 16 * WISH_BONE_FREQ;
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signal last_cnt, max_thres : integer range 0 to 16 * WISHBONE_FREQ;
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signal minpulse, minp, min_thres: integer range 0 to 8 * WISH_BONE_FREQ;
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signal minpulse, minp, min_thres: integer range 0 to 8 * WISHBONE_FREQ;
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signal zspdif, spdif_in, zspdif_in, trans, ztrans : std_logic;
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signal zspdif, spdif_in, zspdif_in, trans, ztrans : std_logic;
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signal trans_cnt : integer range 0 to TRANSITIONS;
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signal trans_cnt : integer range 0 to TRANSITIONS;
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signal valid, p_long, p_short: std_logic;
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signal valid, p_long, p_short: std_logic;
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type pulse_type is (ZERO, SHORT, MED, LONG);
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type pulse_type is (ZERO, SHORT, MED, LONG);
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type pulse_array is array (0 to 3) of pulse_type;
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type pulse_array is array (0 to 3) of pulse_type;
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if mp_cnt < minp then
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if mp_cnt < minp then
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minp <= mp_cnt;
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minp <= mp_cnt;
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end if;
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end if;
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else
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else
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trans <= '0';
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trans <= '0';
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if mp_cnt < 16 * WISH_BONE_FREQ then
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if mp_cnt < 16 * WISHBONE_FREQ then
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mp_cnt <= mp_cnt + 1;
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mp_cnt <= mp_cnt + 1;
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end if;
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end if;
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end if;
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end if;
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-- transition counting
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-- transition counting
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if trans = '1' then
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if trans = '1' then
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-- the max/min pulse length is updated after given # of transitions
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-- the max/min pulse length is updated after given # of transitions
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trans_cnt <= 0;
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trans_cnt <= 0;
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maxpulse <= maxp;
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maxpulse <= maxp;
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maxp <= 0;
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maxp <= 0;
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minpulse <= minp;
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minpulse <= minp;
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minp <= 8 * WISH_BONE_FREQ;
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minp <= 8 * WISHBONE_FREQ;
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min_thres <= maxp / 2;
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min_thres <= maxp / 2;
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if maxp < 11 then
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if maxp < 11 then
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max_thres <= maxp - 1;
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max_thres <= maxp - 1;
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else
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else
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max_thres <= maxp - 3;
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max_thres <= maxp - 3;
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