| Line 44... |
Line 44... |
----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2004/06/13 18:08:50 gedra
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-- Renamed generic and cleaned some lint's
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--
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-- Revision 1.1 2004/06/06 15:43:02 gedra
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-- Revision 1.1 2004/06/06 15:43:02 gedra
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-- Early version of the bi-phase mark decoder.
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-- Early version of the bi-phase mark decoder.
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--
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--
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--
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--
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| Line 73... |
Line 76... |
cs_b_en: out std_logic); -- channel status ch. B enable);
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cs_b_en: out std_logic); -- channel status ch. B enable);
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end rx_phase_det;
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end rx_phase_det;
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architecture rtl of rx_phase_det is
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architecture rtl of rx_phase_det is
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constant TRANSITIONS : integer := 40;
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constant TRANSITIONS : integer := 70;
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constant FRAMES_FOR_LOCK : integer := 3;
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constant FRAMES_FOR_LOCK : integer := 3;
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signal maxpulse, maxp, mp_cnt: integer range 0 to 16 * WISHBONE_FREQ;
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signal maxpulse, maxp, mp_cnt: integer range 0 to 16 * WISHBONE_FREQ;
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signal last_cnt, max_thres : integer range 0 to 16 * WISHBONE_FREQ;
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signal last_cnt, max_thres : integer range 0 to 16 * WISHBONE_FREQ;
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signal minpulse, minp, min_thres: integer range 0 to 8 * WISHBONE_FREQ;
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signal minpulse, minp, min_thres: integer range 0 to 8 * WISHBONE_FREQ;
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signal zspdif, spdif_in, zspdif_in, trans, ztrans : std_logic;
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signal zspdif, spdif_in, zspdif_in, trans, ztrans : std_logic;
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