| Line 43... |
Line 43... |
----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.4 2004/07/12 17:06:41 gedra
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-- Fixed bug with lock event generation.
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--
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-- Revision 1.3 2004/07/11 16:19:50 gedra
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-- Revision 1.3 2004/07/11 16:19:50 gedra
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-- Bug-fix.
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-- Bug-fix.
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--
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--
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-- Revision 1.2 2004/06/27 16:16:55 gedra
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-- Revision 1.2 2004/06/27 16:16:55 gedra
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-- Signal renaming and bug fix.
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-- Signal renaming and bug fix.
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| Line 59... |
Line 62... |
library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use work.rx_package.all;
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use work.rx_package.all;
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entity rx_spdif is
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entity rx_spdif is
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generic (DATA_WIDTH: integer range 16 to 32 := 16;
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generic (DATA_WIDTH: integer range 16 to 32;
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ADDR_WIDTH: integer range 8 to 64 := 8;
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ADDR_WIDTH: integer range 8 to 64;
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CH_ST_CAPTURE: integer range 0 to 8 := 0;
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CH_ST_CAPTURE: integer range 0 to 8;
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WISHBONE_FREQ: natural:= 33);
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WISHBONE_FREQ: natural);
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port (
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port (
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-- Wishbone interface
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-- Wishbone interface
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wb_clk_i: in std_logic;
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wb_clk_i: in std_logic;
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wb_rst_i: in std_logic;
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wb_rst_i: in std_logic;
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wb_sel_i: in std_logic;
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wb_sel_i: in std_logic;
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| Line 120... |
Line 123... |
when wb_adr_i(ADDR_WIDTH - 1) = '0' else sample_dout;
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when wb_adr_i(ADDR_WIDTH - 1) = '0' else sample_dout;
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end generate DB16;
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end generate DB16;
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DB32: if DATA_WIDTH = 32 generate
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DB32: if DATA_WIDTH = 32 generate
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data_out <= ver_dout or conf_dout or stat_dout or imask_dout or istat_dout or
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data_out <= ver_dout or conf_dout or stat_dout or imask_dout or istat_dout or
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cap_dout(1) or cap_dout(2) or cap_dout(3) or cap_dout(4) or
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cap_dout(1) or cap_dout(2) or cap_dout(3) or cap_dout(4) or
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cap_dout(5) or cap_dout(6) or cap_dout(7) when
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cap_dout(5) or cap_dout(6) or cap_dout(7) or cap_dout(0) when
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wb_adr_i(ADDR_WIDTH - 1) = '0' else sample_dout;
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wb_adr_i(ADDR_WIDTH - 1) = '0' else sample_dout;
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end generate DB32;
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end generate DB32;
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-- Wishbone bus cycle decoder
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-- Wishbone bus cycle decoder
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WB: rx_wb_decoder
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WB: rx_wb_decoder
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| Line 274... |
Line 277... |
istat_events(3) <= istat_paritya;
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istat_events(3) <= istat_paritya;
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istat_events(4) <= istat_parityb;
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istat_events(4) <= istat_parityb;
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istat_events(15 downto 5) <= (others => '0');
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istat_events(15 downto 5) <= (others => '0');
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IS32: if DATA_WIDTH = 32 generate
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IS32: if DATA_WIDTH = 32 generate
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istat_events(23 downto 16) <= istat_cap(7 downto 0);
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istat_events(23 downto 16) <= istat_cap(7 downto 0);
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istat_events(32 downto 24) <= (others => '0');
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istat_events(31 downto 24) <= (others => '0');
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end generate IS32;
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end generate IS32;
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-- capture registers
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-- capture registers
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GCAP: if DATA_WIDTH = 32 and CH_ST_CAPTURE > 0 generate
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GCAP: if DATA_WIDTH = 32 and CH_ST_CAPTURE > 0 generate
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CAPR: for k in 0 to CH_ST_CAPTURE - 1 generate
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CAPR: for k in 0 to CH_ST_CAPTURE - 1 generate
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| Line 299... |
Line 302... |
cs_a_en => cs_a_en,
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cs_a_en => cs_a_en,
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cs_b_en => cs_b_en);
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cs_b_en => cs_b_en);
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end generate CAPR;
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end generate CAPR;
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-- unused capture registers set to zero
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-- unused capture registers set to zero
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UCAPR: if CH_ST_CAPTURE < 8 generate
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UCAPR: if CH_ST_CAPTURE < 8 generate
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UC: for k in CH_ST_CAPTURE - 1 to 7 generate
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UC: for k in CH_ST_CAPTURE to 7 generate
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cap_dout(k) <= (others => '0');
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cap_dout(k) <= (others => '0');
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end generate UC;
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end generate UC;
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end generate UCAPR;
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end generate UCAPR;
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end generate GCAP;
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end generate GCAP;
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