| Line 43... |
Line 43... |
----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.5 2004/07/19 16:58:37 gedra
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-- Fixed bug.
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--
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-- Revision 1.4 2004/07/12 17:06:41 gedra
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-- Revision 1.4 2004/07/12 17:06:41 gedra
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-- Fixed bug with lock event generation.
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-- Fixed bug with lock event generation.
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--
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--
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-- Revision 1.3 2004/07/11 16:19:50 gedra
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-- Revision 1.3 2004/07/11 16:19:50 gedra
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-- Bug-fix.
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-- Bug-fix.
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| Line 100... |
Line 103... |
signal status_rd : std_logic;
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signal status_rd : std_logic;
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signal stat_dout: std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal stat_dout: std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal imask_bits, imask_dout: std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal imask_bits, imask_dout: std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal imask_rd, imask_wr : std_logic;
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signal imask_rd, imask_wr : std_logic;
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signal istat_dout, istat_events: std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal istat_dout, istat_events: std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal istat_rd, istat_wr : std_logic;
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signal istat_rd, istat_wr, istat_lock : std_logic;
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signal istat_lock, istat_lsbf, istat_hsbf, istat_paritya, istat_parityb: std_logic;
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signal istat_lsbf, istat_hsbf, istat_paritya, istat_parityb: std_logic;
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signal istat_cap : std_logic_vector(7 downto 0);
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signal istat_cap : std_logic_vector(7 downto 0);
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signal ch_st_cap_rd, ch_st_cap_wr, ch_st_data_rd: std_logic_vector(7 downto 0);
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signal ch_st_cap_rd, ch_st_cap_wr, ch_st_data_rd: std_logic_vector(7 downto 0);
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signal cap_dout : bus_array;
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signal cap_dout : bus_array;
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signal ch_data, ud_a_en, ud_b_en, cs_a_en, cs_b_en: std_logic;
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signal ch_data, ud_a_en, ud_b_en, cs_a_en, cs_b_en: std_logic;
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signal mem_rd, sample_wr : std_logic;
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signal mem_rd, sample_wr : std_logic;
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signal sample_din, sample_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal sample_din, sample_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal sbuf_wr_adr : std_logic_vector(ADDR_WIDTH - 2 downto 0);
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signal sbuf_wr_adr, sbuf_rd_adr : std_logic_vector(ADDR_WIDTH - 2 downto 0);
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signal lock, rx_frame_start: std_logic;
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signal lock, rx_frame_start: std_logic;
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signal rx_data, rx_data_en, rx_block_start: std_logic;
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signal rx_data, rx_data_en, rx_block_start: std_logic;
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signal rx_channel_a, rx_error, lock_evt: std_logic;
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signal rx_channel_a, rx_error, lock_evt: std_logic;
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begin
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begin
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| Line 154... |
Line 157... |
intmask_rd => imask_rd,
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intmask_rd => imask_rd,
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intmask_wr => imask_wr,
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intmask_wr => imask_wr,
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intstat_rd => istat_rd,
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intstat_rd => istat_rd,
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intstat_wr => istat_wr,
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intstat_wr => istat_wr,
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mem_rd => mem_rd,
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mem_rd => mem_rd,
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mem_addr => sbuf_rd_adr,
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ch_st_cap_rd => ch_st_cap_rd,
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ch_st_cap_rd => ch_st_cap_rd,
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ch_st_cap_wr => ch_st_cap_wr,
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ch_st_cap_wr => ch_st_cap_wr,
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ch_st_data_rd => ch_st_data_rd);
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ch_st_data_rd => ch_st_data_rd);
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-- Version register
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-- Version register
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| Line 201... |
Line 205... |
ctrl_wr => config_wr,
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ctrl_wr => config_wr,
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ctrl_rd => config_rd,
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ctrl_rd => config_rd,
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ctrl_din => wb_dat_i,
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ctrl_din => wb_dat_i,
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ctrl_dout => conf_dout,
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ctrl_dout => conf_dout,
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ctrl_bits => conf_bits);
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ctrl_bits => conf_bits);
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conf_mode(3 downto 0) <= "0000";
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conf_paren <= '0';
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conf_staten <= '0';
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conf_useren <= '0';
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conf_valen <= '0';
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end generate CG16;
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end generate CG16;
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conf_blken <= conf_bits(5);
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conf_blken <= conf_bits(5);
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conf_valid <= conf_bits(4);
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conf_valid <= conf_bits(4);
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conf_chas <= conf_bits(3);
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conf_chas <= conf_bits(3);
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evt_en <= conf_bits(2);
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evt_en <= conf_bits(2);
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| Line 320... |
Line 329... |
rst => wb_rst_i,
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rst => wb_rst_i,
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din => sample_din,
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din => sample_din,
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wr_en => sample_wr,
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wr_en => sample_wr,
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rd_en => mem_rd,
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rd_en => mem_rd,
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wr_addr => sbuf_wr_adr,
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wr_addr => sbuf_wr_adr,
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rd_addr => wb_adr_i(ADDR_WIDTH - 2 downto 0),
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rd_addr => sbuf_rd_adr,
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dout => sample_dout);
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dout => sample_dout);
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-- phase decoder
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-- phase decoder
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PDET: rx_phase_det
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PDET: rx_phase_det
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generic map (
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generic map (
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