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[/] [spdif_interface/] [trunk/] [rtl/] [vhdl/] [rx_spdif.vhd] - Diff between revs 62 and 72

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--
 
--
 
-- CVS Revision History
 
-- CVS Revision History
 
--
 
--
 
-- $Log: not supported by cvs2svn $
 
-- $Log: not supported by cvs2svn $
 
 
 
-- Revision 1.6  2004/07/20 17:41:25  gedra
 
 
 
-- Cleaned up synthesis warnings.
 
 
 
--
 
-- Revision 1.5  2004/07/19 16:58:37  gedra
 
-- Revision 1.5  2004/07/19 16:58:37  gedra
 
-- Fixed bug.
 
-- Fixed bug.
 
--
 
--
 
-- Revision 1.4  2004/07/12 17:06:41  gedra
 
-- Revision 1.4  2004/07/12 17:06:41  gedra
 
-- Fixed bug with lock event generation.
 
-- Fixed bug with lock event generation.
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end rx_spdif;
 
end rx_spdif;
 
 
 
 
 
architecture rtl of rx_spdif is
 
architecture rtl of rx_spdif is
 
 
 
 
 
  signal data_out, ver_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
 
  signal data_out, ver_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
 
  signal ver_rd : std_logic;
 
   signal ver_rd, conf_chas, conf_valid               : std_logic;
 
  signal conf_rxen, conf_sample, evt_en, conf_chas, conf_valid : std_logic;
 
   signal conf_rxen, conf_sample, evt_en              : std_logic;
 
  signal conf_blken, conf_valen, conf_useren, conf_staten : std_logic;
 
   signal conf_blken, conf_valen, conf_useren         : std_logic;
 
  signal conf_paren, config_rd, config_wr : std_logic;
 
  signal conf_paren, config_rd, config_wr : std_logic;
 
  signal conf_mode : std_logic_vector(3 downto 0);
 
  signal conf_mode : std_logic_vector(3 downto 0);
 
  signal conf_bits, conf_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
 
  signal conf_bits, conf_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
 
  signal status_rd : std_logic;
 
   signal status_rd, istat_parityb                    : std_logic;
 
  signal stat_dout: std_logic_vector(DATA_WIDTH - 1 downto 0);
 
  signal stat_dout: std_logic_vector(DATA_WIDTH - 1 downto 0);
 
  signal imask_bits, imask_dout: std_logic_vector(DATA_WIDTH - 1 downto 0);
 
  signal imask_bits, imask_dout: std_logic_vector(DATA_WIDTH - 1 downto 0);
 
  signal imask_rd, imask_wr : std_logic;
 
   signal imask_rd, imask_wr, conf_staten             : std_logic;
 
  signal istat_dout, istat_events: std_logic_vector(DATA_WIDTH - 1 downto 0);
 
  signal istat_dout, istat_events: std_logic_vector(DATA_WIDTH - 1 downto 0);
 
  signal istat_rd, istat_wr, istat_lock : std_logic;
 
  signal istat_rd, istat_wr, istat_lock : std_logic;
 
  signal istat_lsbf, istat_hsbf, istat_paritya, istat_parityb: std_logic;
 
   signal istat_lsbf, istat_hsbf, istat_paritya       : std_logic;
 
  signal istat_cap : std_logic_vector(7 downto 0);
 
  signal istat_cap : std_logic_vector(7 downto 0);
 
  signal ch_st_cap_rd, ch_st_cap_wr, ch_st_data_rd: std_logic_vector(7 downto 0);
 
  signal ch_st_cap_rd, ch_st_cap_wr, ch_st_data_rd: std_logic_vector(7 downto 0);
 
  signal cap_dout : bus_array;
 
  signal cap_dout : bus_array;
 
  signal ch_data, ud_a_en, ud_b_en, cs_a_en, cs_b_en: std_logic;
 
  signal ch_data, ud_a_en, ud_b_en, cs_a_en, cs_b_en: std_logic;
 
  signal mem_rd, sample_wr : std_logic;
 
  signal mem_rd, sample_wr : std_logic;
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    conf_paren <= conf_bits(19);
 
    conf_paren <= conf_bits(19);
 
    conf_staten <= conf_bits(18);
 
    conf_staten <= conf_bits(18);
 
    conf_useren <= conf_bits(17);
 
    conf_useren <= conf_bits(17);
 
    conf_valen <= conf_bits(16);
 
    conf_valen <= conf_bits(16);
 
  end generate CG32;
 
  end generate CG32;
 
 
 
 
 
  CG16: if DATA_WIDTH = 16 generate
 
  CG16: if DATA_WIDTH = 16 generate
 
    CONF: gen_control_reg
 
    CONF: gen_control_reg
 
      generic map (
 
      generic map (
 
        DATA_WIDTH => 16,
 
        DATA_WIDTH => 16,
 
        ACTIVE_BIT_MASK => "1111110000000000")
 
        ACTIVE_BIT_MASK => "1111110000000000")
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    conf_paren <= '0';
 
    conf_paren <= '0';
 
    conf_staten <= '0';
 
    conf_staten <= '0';
 
    conf_useren <= '0';
 
    conf_useren <= '0';
 
    conf_valen <= '0';
 
    conf_valen <= '0';
 
  end generate CG16;
 
  end generate CG16;
 
 
 
 
 
  conf_blken <= conf_bits(5);
 
  conf_blken <= conf_bits(5);
 
  conf_valid <= conf_bits(4);
 
  conf_valid <= conf_bits(4);
 
  conf_chas <= conf_bits(3);
 
  conf_chas <= conf_bits(3);
 
  evt_en <= conf_bits(2);
 
  evt_en <= conf_bits(2);
 
  conf_sample <= conf_bits(1);
 
  conf_sample <= conf_bits(1);
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        ctrl_rd => imask_rd,
 
        ctrl_rd => imask_rd,
 
        ctrl_din => wb_dat_i,
 
        ctrl_din => wb_dat_i,
 
        ctrl_dout => imask_dout,
 
        ctrl_dout => imask_dout,
 
        ctrl_bits => imask_bits);
 
        ctrl_bits => imask_bits);
 
  end generate IM32;
 
  end generate IM32;
 
 
 
 
 
  IM16: if DATA_WIDTH = 16 generate
 
  IM16: if DATA_WIDTH = 16 generate
 
    IMASK: gen_control_reg
 
    IMASK: gen_control_reg
 
      generic map (
 
      generic map (
 
        DATA_WIDTH => 16,
 
        DATA_WIDTH => 16,
 
        ACTIVE_BIT_MASK => "1111100000000000")
 
        ACTIVE_BIT_MASK => "1111100000000000")
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      evt_dout => istat_dout,
 
      evt_dout => istat_dout,
 
      event => istat_events,
 
      event => istat_events,
 
      evt_mask => imask_bits,
 
      evt_mask => imask_bits,
 
      evt_en => evt_en,
 
      evt_en => evt_en,
 
      evt_irq => rx_int_o);
 
      evt_irq => rx_int_o);
 
 
 
 
 
  istat_events(0) <= lock_evt;
 
  istat_events(0) <= lock_evt;
 
  istat_events(1) <= istat_lsbf;
 
  istat_events(1) <= istat_lsbf;
 
  istat_events(2) <= istat_hsbf;
 
  istat_events(2) <= istat_hsbf;
 
  istat_events(3) <= istat_paritya;
 
  istat_events(3) <= istat_paritya;
 
  istat_events(4) <= istat_parityb;
 
  istat_events(4) <= istat_parityb;
 
  istat_events(15 downto 5) <= (others => '0');
 
  istat_events(15 downto 5) <= (others => '0');
 
 
 
 
 
  IS32: if DATA_WIDTH = 32 generate
 
  IS32: if DATA_WIDTH = 32 generate
 
    istat_events(23 downto 16) <= istat_cap(7 downto 0);
 
    istat_events(23 downto 16) <= istat_cap(7 downto 0);
 
    istat_events(31 downto 24) <= (others => '0');
 
    istat_events(31 downto 24) <= (others => '0');
 
  end generate IS32;
 
  end generate IS32;
 
 
 
 
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        ud_a_en => ud_a_en,
 
        ud_a_en => ud_a_en,
 
        ud_b_en => ud_b_en,
 
        ud_b_en => ud_b_en,
 
        cs_a_en => cs_a_en,
 
        cs_a_en => cs_a_en,
 
        cs_b_en => cs_b_en);
 
        cs_b_en => cs_b_en);
 
    end generate CAPR;
 
    end generate CAPR;
 
 
 
 
 
    -- unused capture registers set to zero
 
    -- unused capture registers set to zero
 
    UCAPR: if CH_ST_CAPTURE < 8 generate
 
    UCAPR: if CH_ST_CAPTURE < 8 generate
 
      UC: for k in CH_ST_CAPTURE to 7 generate
 
      UC: for k in CH_ST_CAPTURE to 7 generate
 
        cap_dout(k) <= (others => '0');
 
        cap_dout(k) <= (others => '0');
 
      end generate UC;
 
      end generate UC;

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