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----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.1 2004/06/23 18:09:57 gedra
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-- Wishbone bus cycle decoder.
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--
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--
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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--use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity rx_wb_decoder is
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entity rx_wb_decoder is
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generic (DATA_WIDTH: integer;
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generic (DATA_WIDTH: integer;
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ADDR_WIDTH: integer);
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ADDR_WIDTH: integer);
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port (
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port (
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constant REG_RXINTMASK : std_logic_vector(6 downto 0) := "0000011";
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constant REG_RXINTMASK : std_logic_vector(6 downto 0) := "0000011";
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constant REG_RXINTSTAT : std_logic_vector(6 downto 0) := "0000100";
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constant REG_RXINTSTAT : std_logic_vector(6 downto 0) := "0000100";
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signal iack, iwr, ird : std_logic;
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signal iack, iwr, ird : std_logic;
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signal acnt: integer range 0 to 2**(ADDR_WIDTH - 1) - 1;
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signal acnt: integer range 0 to 2**(ADDR_WIDTH - 1) - 1;
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signal all_ones : std_logic_vector(ADDR_WIDTH - 1 downto 0);
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signal all_ones : std_logic_vector(ADDR_WIDTH - 1 downto 0);
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signal rdout : std_logic_vector(DATA_WIDTH - 1 downto 0);
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begin
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begin
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wb_ack_o <= iack;
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wb_ack_o <= iack;
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-- read generation
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-- read generation
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ird <= '1' when wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' and
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ird <= '1' when wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' and
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wb_we_i = '0' else '0';
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wb_we_i = '0' else '0';
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wb_dat_o <= data_out when wb_adr_i(ADDR_WIDTH - 1) = '1' else rdout;
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DREG: process (wb_clk_i) -- clock data from registers
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begin
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if rising_edge(wb_clk_i) then
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rdout <= data_out;
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end if;
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end process DREG;
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-- sample memory read address. This needs special attention due to read latency
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-- sample memory read address. This needs special attention due to read latency
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mem_addr <= CONV_STD_LOGIC_VECTOR(acnt, ADDR_WIDTH - 1) when
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mem_addr <= CONV_STD_LOGIC_VECTOR(acnt, ADDR_WIDTH - 1) when
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wb_cti_i = "010" and wb_we_i = '0' and iack = '1' and
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wb_cti_i = "010" and wb_we_i = '0' and iack = '1' and
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wb_bte_i = "00" else wb_adr_i(ADDR_WIDTH - 2 downto 0);
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wb_bte_i = "00" else wb_adr_i(ADDR_WIDTH - 2 downto 0);
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all_ones <= (others => '1');
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all_ones(ADDR_WIDTH - 1 downto 0) <= (others => '1');
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SMA: process (wb_clk_i, wb_rst_i)
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SMA: process (wb_clk_i, wb_rst_i)
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begin
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begin
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if wb_rst_i = '1' then
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if wb_rst_i = '1' then
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acnt <= 0;
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acnt <= 0;
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