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----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2004/06/24 19:25:03 gedra
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-- Added data output.
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--
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-- Revision 1.1 2004/06/23 18:09:57 gedra
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-- Revision 1.1 2004/06/23 18:09:57 gedra
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-- Wishbone bus cycle decoder.
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-- Wishbone bus cycle decoder.
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--
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--
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--
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--
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library IEEE;
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library ieee;
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use IEEE.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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entity rx_wb_decoder is
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entity rx_wb_decoder is
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generic (DATA_WIDTH: integer;
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generic (DATA_WIDTH: integer;
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ADDR_WIDTH: integer);
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ADDR_WIDTH: integer);
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port (
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port (
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rdout <= data_out;
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rdout <= data_out;
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end if;
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end if;
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end process DREG;
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end process DREG;
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-- sample memory read address. This needs special attention due to read latency
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-- sample memory read address. This needs special attention due to read latency
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mem_addr <= CONV_STD_LOGIC_VECTOR(acnt, ADDR_WIDTH - 1) when
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mem_addr <= std_logic_vector(to_unsigned(acnt, ADDR_WIDTH - 1)) when
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wb_cti_i = "010" and wb_we_i = '0' and iack = '1' and
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wb_cti_i = "010" and wb_we_i = '0' and iack = '1' and
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wb_bte_i = "00" else wb_adr_i(ADDR_WIDTH - 2 downto 0);
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wb_bte_i = "00" else wb_adr_i(ADDR_WIDTH - 2 downto 0);
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all_ones(ADDR_WIDTH - 1 downto 0) <= (others => '1');
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all_ones(ADDR_WIDTH - 1 downto 0) <= (others => '1');
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if wb_cti_i = "010" and wb_we_i = '0' and wb_bte_i = "00" then
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if wb_cti_i = "010" and wb_we_i = '0' and wb_bte_i = "00" then
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if iack = '0' then
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if iack = '0' then
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if wb_adr_i = all_ones then
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if wb_adr_i = all_ones then
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acnt <= 0;
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acnt <= 0;
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else
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else
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acnt <= CONV_INTEGER(wb_adr_i) + 1;
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acnt <= to_integer(unsigned(wb_adr_i)) + 1;
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end if;
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end if;
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else
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else
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if acnt < 2**(ADDR_WIDTH - 1) - 1 then
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if acnt < 2**(ADDR_WIDTH - 1) - 1 then
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acnt <= acnt + 1;
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acnt <= acnt + 1;
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else
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else
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-- capture register strobes
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-- capture register strobes
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CR32: if DATA_WIDTH = 32 generate
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CR32: if DATA_WIDTH = 32 generate
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CRST: for k in 0 to 7 generate
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CRST: for k in 0 to 7 generate
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ch_st_cap_rd(k) <= '1' when ird = '1' and wb_adr_i(6 downto 4) = "001"
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ch_st_cap_rd(k) <= '1' when ird = '1' and wb_adr_i(6 downto 4) = "001"
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and wb_adr_i(3 downto 0) = CONV_STD_LOGIC_VECTOR(2*k,4)
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and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k,4))
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else '0';
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else '0';
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ch_st_cap_wr(k) <= '1' when iwr = '1' and wb_adr_i(6 downto 4) = "001"
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ch_st_cap_wr(k) <= '1' when iwr = '1' and wb_adr_i(6 downto 4) = "001"
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and wb_adr_i(3 downto 0) = CONV_STD_LOGIC_VECTOR(2*k,4)
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and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k,4))
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else '0';
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else '0';
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ch_st_data_rd(k) <= '1' when ird = '1' and wb_adr_i(6 downto 4) = "001"
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ch_st_data_rd(k) <= '1' when ird = '1' and wb_adr_i(6 downto 4) = "001"
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and wb_adr_i(3 downto 0) = CONV_STD_LOGIC_VECTOR(2*k+1,4)
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and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k+1,4))
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else '0';
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else '0';
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end generate CRST;
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end generate CRST;
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end generate CR32;
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end generate CR32;
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CR16: if DATA_WIDTH = 16 generate
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CR16: if DATA_WIDTH = 16 generate
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ch_st_cap_rd(7 downto 0) <= (others => '0');
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ch_st_cap_rd(7 downto 0) <= (others => '0');
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