| Line 43... |
Line 43... |
----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.3 2004/06/26 14:14:47 gedra
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-- Converted to numeric_std and fixed a few bugs.
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--
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-- Revision 1.2 2004/06/24 19:25:03 gedra
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-- Revision 1.2 2004/06/24 19:25:03 gedra
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-- Added data output.
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-- Added data output.
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--
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--
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-- Revision 1.1 2004/06/23 18:09:57 gedra
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-- Revision 1.1 2004/06/23 18:09:57 gedra
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-- Wishbone bus cycle decoder.
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-- Wishbone bus cycle decoder.
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| Line 201... |
Line 204... |
end process SMA;
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end process SMA;
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-- read and write strobe generation
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-- read and write strobe generation
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version_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXVERSION and ird = '1'
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version_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXVERSION and ird = '1'
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else '0';
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and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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config_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXCONFIG and ird = '1'
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config_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXCONFIG and ird = '1'
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else '0';
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and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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config_wr <= '1' when wb_adr_i(6 downto 0) = REG_RXCONFIG and iwr = '1'
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config_wr <= '1' when wb_adr_i(6 downto 0) = REG_RXCONFIG and iwr = '1'
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else '0';
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and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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status_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXSTATUS and ird = '1'
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status_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXSTATUS and ird = '1'
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else '0';
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and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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intmask_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXINTMASK and ird = '1'
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intmask_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXINTMASK and ird = '1'
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else '0';
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and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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intmask_wr <= '1' when wb_adr_i(6 downto 0) = REG_RXINTMASK and iwr = '1'
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intmask_wr <= '1' when wb_adr_i(6 downto 0) = REG_RXINTMASK and iwr = '1'
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else '0';
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and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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intstat_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXINTSTAT and ird = '1'
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intstat_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXINTSTAT and ird = '1'
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else '0';
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and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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intstat_wr <= '1' when wb_adr_i(6 downto 0) = REG_RXINTSTAT and iwr = '1'
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intstat_wr <= '1' when wb_adr_i(6 downto 0) = REG_RXINTSTAT and iwr = '1'
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else '0';
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and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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mem_rd <= '1' when wb_adr_i(ADDR_WIDTH - 1) = '1' and ird = '1' else '0';
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mem_rd <= '1' when wb_adr_i(ADDR_WIDTH - 1) = '1' and ird = '1' else '0';
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-- capture register strobes
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-- capture register strobes
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CR32: if DATA_WIDTH = 32 generate
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CR32: if DATA_WIDTH = 32 generate
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CRST: for k in 0 to 7 generate
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CRST: for k in 0 to 7 generate
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ch_st_cap_rd(k) <= '1' when ird = '1' and wb_adr_i(6 downto 4) = "001"
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ch_st_cap_rd(k) <= '1' when ird = '1' and wb_adr_i(6 downto 4) = "001"
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and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k,4))
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and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k,4))
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else '0';
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and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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ch_st_cap_wr(k) <= '1' when iwr = '1' and wb_adr_i(6 downto 4) = "001"
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ch_st_cap_wr(k) <= '1' when iwr = '1' and wb_adr_i(6 downto 4) = "001"
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and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k,4))
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and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k,4))
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else '0';
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and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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ch_st_data_rd(k) <= '1' when ird = '1' and wb_adr_i(6 downto 4) = "001"
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ch_st_data_rd(k) <= '1' when ird = '1' and wb_adr_i(6 downto 4) = "001"
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and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k+1,4))
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and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k+1,4))
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else '0';
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and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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end generate CRST;
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end generate CRST;
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end generate CR32;
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end generate CR32;
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CR16: if DATA_WIDTH = 16 generate
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CR16: if DATA_WIDTH = 16 generate
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ch_st_cap_rd(7 downto 0) <= (others => '0');
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ch_st_cap_rd(7 downto 0) <= (others => '0');
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ch_st_cap_wr(7 downto 0) <= (others => '0');
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ch_st_cap_wr(7 downto 0) <= (others => '0');
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