| Line 43... |
Line 43... |
----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2004/07/17 17:21:11 gedra
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-- Fixed bug.
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--
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-- Revision 1.1 2004/07/14 17:58:19 gedra
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-- Revision 1.1 2004/07/14 17:58:19 gedra
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-- Transmitter channel status buffer.
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-- Transmitter channel status buffer.
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--
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--
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--
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--
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--
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--
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| Line 67... |
Line 70... |
buf_data_b: out std_logic_vector(191 downto 0));
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buf_data_b: out std_logic_vector(191 downto 0));
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end tx_bitbuf;
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end tx_bitbuf;
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architecture rtl of tx_bitbuf is
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architecture rtl of tx_bitbuf is
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type buf_type is array (0 to 23) of std_logic_vector(7 downto 0);
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signal buffer_a, buffer_b: buf_type;
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begin
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begin
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-- the byte buffer is 192 bits (24 bytes) for each channel
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-- the byte buffer is 192 bits (24 bytes) for each channel
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EB: if ENABLE_BUFFER = 1 generate
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EB: if ENABLE_BUFFER = 1 generate
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WBUF: process (wb_clk_i, wb_rst_i)
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WBUF: process (wb_clk_i, wb_rst_i)
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begin
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begin
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if wb_rst_i = '1' then
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if wb_rst_i = '1' then
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buf_data_a(191 downto 0) <= (others => '0');
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for i in 0 to 23 loop
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buf_data_b(191 downto 0) <= (others => '0');
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buffer_a(i) <= (others => '0');
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buffer_b(i) <= (others => '0');
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end loop;
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elsif rising_edge(wb_clk_i) then
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elsif rising_edge(wb_clk_i) then
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if buf_wr = '1' and to_integer(unsigned(wb_adr_i)) < 24 then
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if buf_wr = '1' and to_integer(unsigned(wb_adr_i)) < 24 then
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buf_data_a(8*to_integer(unsigned(wb_adr_i)) + 7 downto to
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buffer_a(to_integer(unsigned(wb_adr_i))) <= wb_dat_i(7 downto 0);
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8*to_integer(unsigned(wb_adr_i))) <= wb_dat_i(7 downto 0);
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buffer_b(to_integer(unsigned(wb_adr_i))) <= wb_dat_i(15 downto 8);
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buf_data_b(8*to_integer(unsigned(wb_adr_i)) + 7 downto
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8*to_integer(unsigned(wb_adr_i))) <= wb_dat_i(15 downto 8);
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end if;
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end if;
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end if;
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end if;
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end process WBUF;
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end process WBUF;
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VGEN: for k in 0 to 23 generate
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buf_data_a(8 * k + 7 downto 8 * k) <= buffer_a(k);
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buf_data_b(8 * k + 7 downto 8 * k) <= buffer_b(k);
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end generate VGEN;
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end generate EB;
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end generate EB;
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-- if the byte buffer is not enabled, set all bits to zero
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-- if the byte buffer is not enabled, set all bits to zero
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NEB: if ENABLE_BUFFER = 0 generate
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NEB: if ENABLE_BUFFER = 0 generate
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buf_data_a(191 downto 0) <= (others => '0');
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buf_data_a(191 downto 0) <= (others => '0');
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