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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.1 2004/07/13 18:30:25 gedra
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-- Transmitter component declarations.
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--
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--
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--
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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package tx_package is
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package tx_package is
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-- type declarations
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-- components used in the transmitter
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type bus_array is array (0 to 7) of std_logic_vector(31 downto 0);
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-- components
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component gen_control_reg
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component gen_control_reg
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generic (DATA_WIDTH: integer;
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generic (DATA_WIDTH: integer;
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-- note that this vector is (0 to xx), reverse order
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-- note that this vector is (0 to xx), reverse order
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ACTIVE_BIT_MASK: std_logic_vector);
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ACTIVE_BIT_MASK: std_logic_vector);
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intmask_rd: out std_logic; -- Interrupt mask register read
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intmask_rd: out std_logic; -- Interrupt mask register read
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intmask_wr: out std_logic; -- Interrupt mask register write
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intmask_wr: out std_logic; -- Interrupt mask register write
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intstat_rd: out std_logic; -- Interrupt status register read
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intstat_rd: out std_logic; -- Interrupt status register read
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intstat_wr: out std_logic; -- Interrupt status register read
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intstat_wr: out std_logic; -- Interrupt status register read
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mem_wr: out std_logic; -- Sample memory write
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mem_wr: out std_logic; -- Sample memory write
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mem_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0); -- mem. addr.
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user_data_wr: out std_logic; -- User data write
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user_data_wr: out std_logic_vector(23 downto 0); -- User data write
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ch_status_wr: out std_logic); -- Ch. status write
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ch_status_wr: out std_logic_vector(23 downto 0)); -- Ch. status write
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end component;
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component tx_ver_reg
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generic (DATA_WIDTH: integer;
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ADDR_WIDTH: integer;
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USER_DATA_BUF: integer;
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CH_STAT_BUF: integer);
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port (
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ver_rd: in std_logic; -- version register read
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ver_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));
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end component;
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component tx_bitbuf
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generic (ENABLE_BUFFER: integer range 0 to 1);
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port (
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wb_clk_i: in std_logic; -- clock
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wb_rst_i: in std_logic; -- reset
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buf_wr: in std_logic; -- buffer write strobe
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wb_adr_i: in std_logic_vector(4 downto 0); -- address
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wb_dat_i: in std_logic_vector(15 downto 0); -- data
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buf_data_a: out std_logic_vector(191 downto 0);
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buf_data_b: out std_logic_vector(191 downto 0));
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end component;
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end component;
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end tx_package;
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end tx_package;
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