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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`include "spi_defines.v"
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`include "spi_defines.v"
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`include "timescale.v"
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`include "timescale.v"
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module spi_shift (clk, rst, latch, len, lsb, go,
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module spi_shift (clk, rst, latch_h, latch_l, len, lsb, go,
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pos_edge, neg_edge, rx_negedge, tx_negedge,
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pos_edge, neg_edge, rx_negedge, tx_negedge,
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tip, last,
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tip, last,
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p_in, p_out, s_clk, s_in, s_out);
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p_in, p_out, s_clk, s_in, s_out);
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parameter Tp = 1;
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parameter Tp = 1;
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input clk; // system clock
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input clk; // system clock
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input rst; // reset
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input rst; // reset
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input latch; // latch signal for storing the data in shift register
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input latch_h; // latch_h signal for storing the data in shift register
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input latch_l; // latch_l signal for storing the data in shift register
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input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
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input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
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input lsb; // lbs first on the line
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input lsb; // lbs first on the line
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input go; // start stansfer
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input go; // start stansfer
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input pos_edge; // recognize posedge of sclk
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input pos_edge; // recognize posedge of sclk
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input neg_edge; // recognize negedge of sclk
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input neg_edge; // recognize negedge of sclk
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input rx_negedge; // s_in is sampled on negative edge
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input rx_negedge; // s_in is sampled on negative edge
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input tx_negedge; // s_out is driven on negative edge
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input tx_negedge; // s_out is driven on negative edge
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output tip; // transfer in progress
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output tip; // transfer in progress
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output last; // last bit
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output last; // last bit
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input [`SPI_MAX_CHAR-1:0] p_in; // parallel in
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input [31:0] p_in; // parallel in
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output [`SPI_MAX_CHAR-1:0] p_out; // parallel out
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output [`SPI_MAX_CHAR-1:0] p_out; // parallel out
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input s_clk; // serial clock
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input s_clk; // serial clock
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input s_in; // serial in
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input s_in; // serial in
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output s_out; // serial out
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output s_out; // serial out
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// Receiving bits from the line
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// Receiving bits from the line
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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data <= #Tp {`SPI_MAX_CHAR{1'b0}};
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data <= #Tp {`SPI_MAX_CHAR{1'b0}};
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else if (latch && !tip)
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`ifdef SPI_MAX_CHAR_64
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data <= #Tp p_in;
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else if (latch_l && !tip)
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data[31:0] <= #Tp p_in[31:0];
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else if (latch_h && !tip)
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data[63:32] <= #Tp p_in[31:0];
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`else
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else if (latch_l && !tip)
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data <= #Tp p_in[`SPI_MAX_CHAR-1:0];
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`endif
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else
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else
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data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
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data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
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end
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end
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endmodule
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endmodule
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