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[/] [spi/] [tags/] [asyst_3/] [rtl/] [verilog/] [spi_shift.v] - Diff between revs 9 and 13

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Rev 9 Rev 13
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
`include "spi_defines.v"
`include "spi_defines.v"
`include "timescale.v"
`include "timescale.v"
 
 
module spi_shift (clk, rst, latch, len, lsb, go,
module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
                  pos_edge, neg_edge, rx_negedge, tx_negedge,
                  pos_edge, neg_edge, rx_negedge, tx_negedge,
                  tip, last,
                  tip, last,
                  p_in, p_out, s_clk, s_in, s_out);
                  p_in, p_out, s_clk, s_in, s_out);
 
 
  parameter Tp = 1;
  parameter Tp = 1;
 
 
  input                          clk;          // system clock
  input                          clk;          // system clock
  input                          rst;          // reset
  input                          rst;          // reset
  input                    [3:0] latch;        // latch signal for storing the data in shift register
  input                    [3:0] latch;        // latch signal for storing the data in shift register
 
  input                    [3:0] byte_sel;     // byte select signals for storing the data in shift register
  input [`SPI_CHAR_LEN_BITS-1:0] len;          // data len in bits (minus one)
  input [`SPI_CHAR_LEN_BITS-1:0] len;          // data len in bits (minus one)
  input                          lsb;          // lbs first on the line
  input                          lsb;          // lbs first on the line
  input                          go;           // start stansfer
  input                          go;           // start stansfer
  input                          pos_edge;     // recognize posedge of sclk
  input                          pos_edge;     // recognize posedge of sclk
  input                          neg_edge;     // recognize negedge of sclk
  input                          neg_edge;     // recognize negedge of sclk
Line 126... Line 127...
  begin
  begin
    if (rst)
    if (rst)
      data   <= #Tp {`SPI_MAX_CHAR{1'b0}};
      data   <= #Tp {`SPI_MAX_CHAR{1'b0}};
`ifdef SPI_MAX_CHAR_128
`ifdef SPI_MAX_CHAR_128
    else if (latch[0] && !tip)
    else if (latch[0] && !tip)
      data[31:0] <= #Tp p_in[31:0];
      begin
 
        if (byte_sel[0])
 
          data[31:24] <= #Tp p_in[31:24];
 
        if (byte_sel[1])
 
          data[23:16] <= #Tp p_in[23:16];
 
        if (byte_sel[2])
 
          data[15:8] <= #Tp p_in[15:8];
 
        if (byte_sel[3])
 
          data[7:0] <= #Tp p_in[7:0];
 
      end
    else if (latch[1] && !tip)
    else if (latch[1] && !tip)
      data[63:32] <= #Tp p_in[31:0];
      begin
 
        if (byte_sel[0])
 
          data[63:56] <= #Tp p_in[31:24];
 
        if (byte_sel[1])
 
          data[55:48] <= #Tp p_in[23:16];
 
        if (byte_sel[2])
 
          data[47:40] <= #Tp p_in[15:8];
 
        if (byte_sel[3])
 
          data[39:32] <= #Tp p_in[7:0];
 
      end
    else if (latch[2] && !tip)
    else if (latch[2] && !tip)
      data[95:64] <= #Tp p_in[31:0];
      begin
 
        if (byte_sel[0])
 
          data[95:88] <= #Tp p_in[31:24];
 
        if (byte_sel[1])
 
          data[87:80] <= #Tp p_in[23:16];
 
        if (byte_sel[2])
 
          data[79:72] <= #Tp p_in[15:8];
 
        if (byte_sel[3])
 
          data[71:64] <= #Tp p_in[7:0];
 
      end
     else if (latch[3] && !tip)
     else if (latch[3] && !tip)
      data[127:96] <= #Tp p_in[31:0];
      begin
 
        if (byte_sel[0])
 
          data[127:120] <= #Tp p_in[31:24];
 
        if (byte_sel[1])
 
          data[119:112] <= #Tp p_in[23:16];
 
        if (byte_sel[2])
 
          data[111:104] <= #Tp p_in[15:8];
 
        if (byte_sel[3])
 
          data[103:96] <= #Tp p_in[7:0];
 
      end
`else
`else
`ifdef SPI_MAX_CHAR_64
`ifdef SPI_MAX_CHAR_64
    else if (latch[0] && !tip)
    else if (latch[0] && !tip)
      data[31:0] <= #Tp p_in[31:0];
      begin
 
        if (byte_sel[0])
 
          data[31:24] <= #Tp p_in[31:24];
 
        if (byte_sel[1])
 
          data[23:16] <= #Tp p_in[23:16];
 
        if (byte_sel[2])
 
          data[15:8] <= #Tp p_in[15:8];
 
        if (byte_sel[3])
 
          data[7:0] <= #Tp p_in[7:0];
 
      end
    else if (latch[1] && !tip)
    else if (latch[1] && !tip)
      data[63:32] <= #Tp p_in[31:0];
      begin
 
        if (byte_sel[0])
 
          data[63:56] <= #Tp p_in[31:24];
 
        if (byte_sel[1])
 
          data[55:48] <= #Tp p_in[23:16];
 
        if (byte_sel[2])
 
          data[47:40] <= #Tp p_in[15:8];
 
        if (byte_sel[3])
 
          data[39:32] <= #Tp p_in[7:0];
 
      end
`else
`else
    else if (latch[0] && !tip)
    else if (latch[0] && !tip)
      data <= #Tp p_in[`SPI_MAX_CHAR-1:0];
      data <= #Tp p_in[`SPI_MAX_CHAR-1:0];
 
      begin
 
      `ifdef `SPI_MAX_CHAR_8
 
        if (byte_sel[3])
 
          data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0];
 
      `endif
 
      `ifdef `SPI_MAX_CHAR_16
 
        if (byte_sel[3])
 
          data[7:0] <= #Tp p_in[7:0];
 
        if (byte_sel[2])
 
          data[15:8] <= #Tp p_in[15:8];
 
      `endif
 
      `ifdef `SPI_MAX_CHAR_32
 
        if (byte_sel[3])
 
          data[7:0] <= #Tp p_in[7:0];
 
        if (byte_sel[2])
 
          data[15:8] <= #Tp p_in[15:8];
 
        if (byte_sel[1])
 
          data[23:16] <= #Tp p_in[23:16];
 
        if (byte_sel[0])
 
          data[31:24] <= #Tp p_in[31:24];
 
      end
 
      `endif
`endif
`endif
`endif
`endif
    else
    else
      data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
      data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
  end
  end

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