OpenCores
URL https://opencores.org/ocsvn/spi/spi/trunk

Subversion Repositories spi

[/] [spi/] [tags/] [asyst_3/] [rtl/] [verilog/] [spi_shift.v] - Diff between revs 7 and 9

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 7 Rev 9
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
`include "spi_defines.v"
`include "spi_defines.v"
`include "timescale.v"
`include "timescale.v"
 
 
module spi_shift (clk, rst, latch_h, latch_l, len, lsb, go,
module spi_shift (clk, rst, latch, len, lsb, go,
                  pos_edge, neg_edge, rx_negedge, tx_negedge,
                  pos_edge, neg_edge, rx_negedge, tx_negedge,
                  tip, last,
                  tip, last,
                  p_in, p_out, s_clk, s_in, s_out);
                  p_in, p_out, s_clk, s_in, s_out);
 
 
  parameter Tp = 1;
  parameter Tp = 1;
 
 
  input                          clk;          // system clock
  input                          clk;          // system clock
  input                          rst;          // reset
  input                          rst;          // reset
  input                          latch_h;      // latch_h signal for storing the data in shift register
  input                    [3:0] latch;        // latch signal for storing the data in shift register
  input                          latch_l;      // latch_l signal for storing the data in shift register
 
  input [`SPI_CHAR_LEN_BITS-1:0] len;          // data len in bits (minus one)
  input [`SPI_CHAR_LEN_BITS-1:0] len;          // data len in bits (minus one)
  input                          lsb;          // lbs first on the line
  input                          lsb;          // lbs first on the line
  input                          go;           // start stansfer
  input                          go;           // start stansfer
  input                          pos_edge;     // recognize posedge of sclk
  input                          pos_edge;     // recognize posedge of sclk
  input                          neg_edge;     // recognize negedge of sclk
  input                          neg_edge;     // recognize negedge of sclk
Line 125... Line 124...
  // Receiving bits from the line
  // Receiving bits from the line
  always @(posedge clk or posedge rst)
  always @(posedge clk or posedge rst)
  begin
  begin
    if (rst)
    if (rst)
      data   <= #Tp {`SPI_MAX_CHAR{1'b0}};
      data   <= #Tp {`SPI_MAX_CHAR{1'b0}};
 
`ifdef SPI_MAX_CHAR_128
 
    else if (latch[0] && !tip)
 
      data[31:0] <= #Tp p_in[31:0];
 
    else if (latch[1] && !tip)
 
      data[63:32] <= #Tp p_in[31:0];
 
    else if (latch[2] && !tip)
 
      data[95:64] <= #Tp p_in[31:0];
 
     else if (latch[3] && !tip)
 
      data[127:96] <= #Tp p_in[31:0];
 
`else
`ifdef SPI_MAX_CHAR_64
`ifdef SPI_MAX_CHAR_64
    else if (latch_l && !tip)
    else if (latch[0] && !tip)
      data[31:0] <= #Tp p_in[31:0];
      data[31:0] <= #Tp p_in[31:0];
    else if (latch_h && !tip)
    else if (latch[1] && !tip)
      data[63:32] <= #Tp p_in[31:0];
      data[63:32] <= #Tp p_in[31:0];
`else
`else
    else if (latch_l && !tip)
    else if (latch[0] && !tip)
      data <= #Tp p_in[`SPI_MAX_CHAR-1:0];
      data <= #Tp p_in[`SPI_MAX_CHAR-1:0];
`endif
`endif
 
`endif
    else
    else
      data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
      data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
  end
  end
 
 
endmodule
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.