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[/] [spi/] [tags/] [rel_5/] [rtl/] [verilog/] [spi_shift.v] - Diff between revs 13 and 15
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Rev 13 |
Rev 15 |
Line 206... |
Line 206... |
`endif
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`endif
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`ifdef `SPI_MAX_CHAR_16
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`ifdef `SPI_MAX_CHAR_16
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if (byte_sel[3])
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if (byte_sel[3])
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data[7:0] <= #Tp p_in[7:0];
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data[7:0] <= #Tp p_in[7:0];
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if (byte_sel[2])
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if (byte_sel[2])
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data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8];
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`endif
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`ifdef `SPI_MAX_CHAR_24
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if (byte_sel[3])
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data[7:0] <= #Tp p_in[7:0];
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if (byte_sel[2])
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data[15:8] <= #Tp p_in[15:8];
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data[15:8] <= #Tp p_in[15:8];
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if (byte_sel[1])
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data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16];
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`endif
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`endif
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`ifdef `SPI_MAX_CHAR_32
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`ifdef `SPI_MAX_CHAR_32
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if (byte_sel[3])
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if (byte_sel[3])
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data[7:0] <= #Tp p_in[7:0];
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data[7:0] <= #Tp p_in[7:0];
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if (byte_sel[2])
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if (byte_sel[2])
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data[15:8] <= #Tp p_in[15:8];
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data[15:8] <= #Tp p_in[15:8];
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if (byte_sel[1])
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if (byte_sel[1])
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data[23:16] <= #Tp p_in[23:16];
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data[23:16] <= #Tp p_in[23:16];
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if (byte_sel[0])
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if (byte_sel[0])
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data[31:24] <= #Tp p_in[31:24];
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data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24];
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end
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`endif
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`endif
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end
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`endif
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`endif
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`endif
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`endif
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else
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else
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data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
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data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
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end
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end
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