Line 336... |
Line 336... |
else if (q == 32'hf7b3d591)
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else if (q == 32'hf7b3d591)
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$display("status: %t transfer completed: 0xf7b3d591 != 0x%x 0x01234567 == 0x%x nok", $time, i_spi_slave.data, q);
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$display("status: %t transfer completed: 0xf7b3d591 != 0x%x 0x01234567 == 0x%x nok", $time, i_spi_slave.data, q);
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else
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else
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$display("status: %t transfer completed: 0xf7b3d591 != 0x%x 0x01234567 != 0x%x nok", $time, i_spi_slave.data, q);
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$display("status: %t transfer completed: 0xf7b3d591 != 0x%x 0x01234567 != 0x%x nok", $time, i_spi_slave.data, q);
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i_wb_master.wb_write(0, SPI_TX_L, 32'hffeeddcc);
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i_wb_master.wb_write(0, SPI_TX_H, 32'hbbaa9988);
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i_wb_master.wb_write(0, SPI_CTRL, 32'he06); // ass, set 64 bit transfer, ie, lsb, rx negedge, tx negedge
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i_wb_master.wb_write(0, SPI_CTRL, 32'he07); // set 64 bit transfer, start transfer
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$display("status: %t generate transfer: 64 bit (0xffeeddccbbaa9988), ass, msb first, tx negedge, rx negedge", $time);
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// Check interrupt signal
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while (!int)
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@(posedge clk);
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i_wb_master.wb_read(1, SPI_RX_H, q);
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@(posedge clk);
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if (int)
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$display("status: %t transfer completed: interrupt still active nok", $time, i_spi_slave.data, q);
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if (i_spi_slave.data == 32'h119955dd && q == 32'hffeeddcc)
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$display("status: %t transfer completed: 0x119955dd == 0x%x 0xffeeddcc == 0x%x ok", $time, i_spi_slave.data, q);
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else if (i_spi_slave.data == 32'h119955dd)
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$display("status: %t transfer completed: 0x119955dd == 0x%x 0xffeeddcc != 0x%x nok", $time, i_spi_slave.data, q);
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else if (q == 32'h119955dd)
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$display("status: %t transfer completed: 0x119955dd != 0x%x 0xffeeddcc == 0x%x nok", $time, i_spi_slave.data, q);
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else
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$display("status: %t transfer completed: 0x119955dd != 0x%x 0xffeeddcc != 0x%x nok", $time, i_spi_slave.data, q);
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$display("\n\nstatus: %t Testbench done", $time);
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$display("\n\nstatus: %t Testbench done", $time);
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#25000; // wait 25us
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#25000; // wait 25us
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$stop;
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$stop;
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