OpenCores
URL https://opencores.org/ocsvn/spi/spi/trunk

Subversion Repositories spi

[/] [spi/] [trunk/] [rtl/] [verilog/] [spi_defines.v] - Diff between revs 9 and 13

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 9 Rev 13
Line 41... Line 41...
//
//
// Number of bits used for devider register. If used in system with
// Number of bits used for devider register. If used in system with
// low frequency of system clock this can be reduced.
// low frequency of system clock this can be reduced.
// Default is 16.
// Default is 16.
//
//
`define SPI_DIVIDER_BIT_NB      16
//`define SPI_DIVIDER_LEN_8
 
`define SPI_DIVIDER_LEN_16
 
//`define SPI_DIVIDER_LEN_32
 
 
//
//
// Maximum nuber of bits that can be send/received at once. Alloved values are
// Maximum nuber of bits that can be send/received at once. 
// 128, 64, 32, 16 and 8. SPI_CHAR_LEN_BITS must be also set to 7, 6, 5, 4 or 3 respectively.
//
// Default is 128.
`define SPI_MAX_CHAR_128
// If SPI_MAX_CHAR is 64 or 128, SPI_MAX_CHAR_64 or SPI_MAX_CHAR_128 must be defined, 
//`define SPI_MAX_CHAR_64
// otherwise comment it out.
//`define SPI_MAX_CHAR_32
//
//`define SPI_MAX_CHAR_16
`define SPI_MAX_CHAR_128        1
//`define SPI_MAX_CHAR_8
//`define SPI_MAX_CHAR_64         1
 
`define SPI_MAX_CHAR            128
 
`define SPI_CHAR_LEN_BITS       7
 
 
 
//
//
// Number of device select signals.
// Number of device select signals.
//
//
`define SPI_SS_NB               8
`define SPI_SS_NB_8
 
//`define SPI_SS_NB_16
 
//`define SPI_SS_NB_32
 
 
//
//
// Bits of WISHBONE address used for partial decoding of SPI registers.
// Bits of WISHBONE address used for partial decoding of SPI registers.
//
//
`define SPI_OFS_BITS              4:2
`define SPI_OFS_BITS              4:2
 
 
Line 96... Line 98...
`define SPI_CTRL_TX_NEGEDGE     2
`define SPI_CTRL_TX_NEGEDGE     2
`define SPI_CTRL_RX_NEGEDGE     1
`define SPI_CTRL_RX_NEGEDGE     1
`define SPI_CTRL_GO             0
`define SPI_CTRL_GO             0
 
 
 
 
 
`ifdef SPI_DIVIDER_LEN_8
 
  `define SPI_DIVIDER_LEN       8
 
`endif
 
`ifdef SPI_DIVIDER_LEN_16
 
  `define SPI_DIVIDER_LEN       16
 
`endif
 
`ifdef SPI_DIVIDER_LEN_32
 
  `define SPI_DIVIDER_LEN       32
 
`endif
 
 
 
`ifdef SPI_MAX_CHAR_128
 
  `define SPI_MAX_CHAR          128
 
  `define SPI_CHAR_LEN_BITS     7
 
`endif
 
`ifdef SPI_MAX_CHAR_64
 
  `define SPI_MAX_CHAR          64
 
  `define SPI_CHAR_LEN_BITS     6
 
`endif
 
`ifdef SPI_MAX_CHAR_32
 
  `define SPI_MAX_CHAR          32
 
  `define SPI_CHAR_LEN_BITS     5
 
`endif
 
`ifdef SPI_MAX_CHAR_16
 
  `define SPI_MAX_CHAR          16
 
  `define SPI_CHAR_LEN_BITS     4
 
`endif
 
`ifdef SPI_MAX_CHAR_8
 
  `define SPI_MAX_CHAR          8
 
  `define SPI_CHAR_LEN_BITS     3
 
`endif
 
 
 
`ifdef SPI_SS_NB_8
 
  `define SPI_SS_NB             8
 
`endif
 
`ifdef SPI_SS_NB_16
 
  `define SPI_SS_NB             16
 
`endif
 
`ifdef SPI_SS_NB_32
 
  `define SPI_SS_NB             32
 
`endif
 
 
 
 
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.