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[/] [spi/] [trunk/] [rtl/] [verilog/] [spi_top.v] - Diff between revs 15 and 21

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Rev 15 Rev 21
Line 176... Line 176... 
    if (wb_rst_i)
 
    if (wb_rst_i)
 
        divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}};
 
        divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}};
 
    else if (spi_divider_sel && wb_we_i && !tip)
 
    else if (spi_divider_sel && wb_we_i && !tip)
 
      begin
 
      begin
 
      `ifdef SPI_DIVIDER_LEN_8
 
      `ifdef SPI_DIVIDER_LEN_8
 
        if (wb_sel_i[3])
 
        if (wb_sel_i[0])
 
          divider <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:0];
 
          divider <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:0];
 
      `endif
 
      `endif
 
      `ifdef SPI_DIVIDER_LEN_16
 
      `ifdef SPI_DIVIDER_LEN_16
 
        if (wb_sel_i[3])
 
        if (wb_sel_i[0])
 
          divider[7:0] <= #Tp wb_dat_i[7:0];
 
          divider[7:0] <= #Tp wb_dat_i[7:0];
 
        if (wb_sel_i[2])
 
        if (wb_sel_i[1])
 
          divider[`SPI_DIVIDER_LEN-1:8] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:8];
 
          divider[`SPI_DIVIDER_LEN-1:8] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:8];
 
      `endif
 
      `endif
 
      `ifdef SPI_DIVIDER_LEN_24
 
      `ifdef SPI_DIVIDER_LEN_24
 
        if (wb_sel_i[3])
 
        if (wb_sel_i[0])
 
          divider[7:0] <= #Tp wb_dat_i[7:0];
 
          divider[7:0] <= #Tp wb_dat_i[7:0];
 
        if (wb_sel_i[2])
 
 
 
          divider[15:8] <= #Tp wb_dat_i[15:8];
 
 
 
        if (wb_sel_i[1])
 
        if (wb_sel_i[1])
 
 
 
          divider[15:8] <= #Tp wb_dat_i[15:8];
 
 
 
        if (wb_sel_i[2])
 
          divider[`SPI_DIVIDER_LEN-1:16] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:16];
 
          divider[`SPI_DIVIDER_LEN-1:16] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:16];
 
      `endif
 
      `endif
 
      `ifdef SPI_DIVIDER_LEN_32
 
      `ifdef SPI_DIVIDER_LEN_32
 
        if (wb_sel_i[3])
 
        if (wb_sel_i[0])
 
          divider[7:0] <= #Tp wb_dat_i[7:0];
 
          divider[7:0] <= #Tp wb_dat_i[7:0];
 
        if (wb_sel_i[2])
 
 
 
          divider[15:8] <= #Tp wb_dat_i[15:8];
 
 
 
        if (wb_sel_i[1])
 
        if (wb_sel_i[1])
 
 
 
          divider[15:8] <= #Tp wb_dat_i[15:8];
 
 
 
        if (wb_sel_i[2])
 
          divider[23:16] <= #Tp wb_dat_i[23:16];
 
          divider[23:16] <= #Tp wb_dat_i[23:16];
 
        if (wb_sel_i[0])
 
        if (wb_sel_i[3])
 
          divider[`SPI_DIVIDER_LEN-1:24] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:24];
 
          divider[`SPI_DIVIDER_LEN-1:24] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:24];
 
      `endif
 
      `endif
 
      end
 
      end
 
  end
 
  end
 
 
 
 
Line 213... Line 213... 
  begin
 
  begin
 
    if (wb_rst_i)
 
    if (wb_rst_i)
 
      ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}};
 
      ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}};
 
    else if(spi_ctrl_sel && wb_we_i && !tip)
 
    else if(spi_ctrl_sel && wb_we_i && !tip)
 
      begin
 
      begin
 
        if (wb_sel_i[3])
 
        if (wb_sel_i[0])
 
          ctrl[7:0] <= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]};
 
          ctrl[7:0] <= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]};
 
        if (wb_sel_i[2])
 
        if (wb_sel_i[1])
 
          ctrl[`SPI_CTRL_BIT_NB-1:8] <= #Tp wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
 
          ctrl[`SPI_CTRL_BIT_NB-1:8] <= #Tp wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
 
      end
 
      end
 
    else if(tip && last_bit && pos_edge)
 
    else if(tip && last_bit && pos_edge)
 
      ctrl[`SPI_CTRL_GO] <= #Tp 1'b0;
 
      ctrl[`SPI_CTRL_GO] <= #Tp 1'b0;
 
  end
 
  end
Line 238... Line 238... 
    if (wb_rst_i)
 
    if (wb_rst_i)
 
      ss <= #Tp {`SPI_SS_NB{1'b0}};
 
      ss <= #Tp {`SPI_SS_NB{1'b0}};
 
    else if(spi_ss_sel && wb_we_i && !tip)
 
    else if(spi_ss_sel && wb_we_i && !tip)
 
      begin
 
      begin
 
      `ifdef SPI_SS_NB_8
 
      `ifdef SPI_SS_NB_8
 
        if (wb_sel_i[3])
 
        if (wb_sel_i[0])
 
          ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0];
 
          ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0];
 
      `endif
 
      `endif
 
      `ifdef SPI_SS_NB_16
 
      `ifdef SPI_SS_NB_16
 
        if (wb_sel_i[3])
 
        if (wb_sel_i[0])
 
          ss[7:0] <= #Tp wb_dat_i[7:0];
 
          ss[7:0] <= #Tp wb_dat_i[7:0];
 
        if (wb_sel_i[2])
 
        if (wb_sel_i[1])
 
          ss[`SPI_SS_NB-1:8] <= #Tp wb_dat_i[`SPI_SS_NB-1:8];
 
          ss[`SPI_SS_NB-1:8] <= #Tp wb_dat_i[`SPI_SS_NB-1:8];
 
      `endif
 
      `endif
 
      `ifdef SPI_SS_NB_24
 
      `ifdef SPI_SS_NB_24
 
        if (wb_sel_i[3])
 
        if (wb_sel_i[0])
 
          ss[7:0] <= #Tp wb_dat_i[7:0];
 
          ss[7:0] <= #Tp wb_dat_i[7:0];
 
        if (wb_sel_i[2])
 
 
 
          ss[15:8] <= #Tp wb_dat_i[15:8];
 
 
 
        if (wb_sel_i[1])
 
        if (wb_sel_i[1])
 
 
 
          ss[15:8] <= #Tp wb_dat_i[15:8];
 
 
 
        if (wb_sel_i[2])
 
          ss[`SPI_SS_NB-1:16] <= #Tp wb_dat_i[`SPI_SS_NB-1:16];
 
          ss[`SPI_SS_NB-1:16] <= #Tp wb_dat_i[`SPI_SS_NB-1:16];
 
      `endif
 
      `endif
 
      `ifdef SPI_SS_NB_32
 
      `ifdef SPI_SS_NB_32
 
        if (wb_sel_i[3])
 
        if (wb_sel_i[0])
 
          ss[7:0] <= #Tp wb_dat_i[7:0];
 
          ss[7:0] <= #Tp wb_dat_i[7:0];
 
        if (wb_sel_i[2])
 
 
 
          ss[15:8] <= #Tp wb_dat_i[15:8];
 
 
 
        if (wb_sel_i[1])
 
        if (wb_sel_i[1])
 
 
 
          ss[15:8] <= #Tp wb_dat_i[15:8];
 
 
 
        if (wb_sel_i[2])
 
          ss[23:16] <= #Tp wb_dat_i[23:16];
 
          ss[23:16] <= #Tp wb_dat_i[23:16];
 
        if (wb_sel_i[0])
 
        if (wb_sel_i[3])
 
          ss[`SPI_SS_NB-1:24] <= #Tp wb_dat_i[`SPI_SS_NB-1:24];
 
          ss[`SPI_SS_NB-1:24] <= #Tp wb_dat_i[`SPI_SS_NB-1:24];
 
      `endif
 
      `endif
 
      end
 
      end
 
  end
 
  end
 
 
 
 

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