URL https://opencores.org/ocsvn/spi_boot/spi_boot/trunk

Subversion Repositories spi_boot

[/] [spi_boot/] [tags/] [rel_1_0_rev_A/] [README] - Diff between revs 18 and 21

Rev 18	Rev 21
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`README for the spi_boot core`	`README for the spi_boot core`
`============================`	`============================`
`Version: $Date: 2005-02-18 06:54:36 $`	`Version: $Date: 2005-02-20 13:13:24 $`


`Description`	`Description`
`-----------`	`-----------`

Line 78...	Line 78...
`\-- sim`	`\-- sim`
`\|`	`\|`
`\-- rtl_sim : Directory for running simulations.`	`\-- rtl_sim : Directory for running simulations.`


	`RAM Loader`
	`----------`

	`Directory rtl/vhdl/ram_loader contains the sample design which loads the next`
	`image from the card and stores its contents to external asynchronous`
	`RAM. After reading 64 KB it triggers a new configuration process for the final`
	`FPGA design.`
	`Refer to the code for the mechanisms involved.`


`Compiling the VHDL Code`	`Compiling the VHDL Code`
`-----------------------`	`-----------------------`

`VHDL compilation and simulation tasks take place inside in sim/rtl_sim`	`VHDL compilation and simulation tasks take place inside in sim/rtl_sim`
`directory. The project setup supports only the GHDL simulator (see`	`directory. The project setup supports only the GHDL simulator (see`