OpenCores
URL https://opencores.org/ocsvn/spi_boot/spi_boot/trunk

Subversion Repositories spi_boot

[/] [spi_boot/] [trunk/] [bench/] [vhdl/] [tb_elem.vhd] - Diff between revs 15 and 16

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 15 Rev 16
Line 1... Line 1...
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- SD/MMC Bootloader
-- SD/MMC Bootloader
-- Generic testbench element for a specific feature set
-- Generic testbench element for a specific feature set
--
--
-- $Id: tb_elem.vhd,v 1.3 2005-02-16 19:34:56 arniml Exp $
-- $Id: tb_elem.vhd,v 1.4 2005-02-17 18:59:23 arniml Exp $
--
--
-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
--
--
-- All rights reserved, see COPYING.
-- All rights reserved, see COPYING.
--
--
Line 236... Line 236...
    rise_clk(1);
    rise_clk(1);
    cfg_init_n_s <= '0';
    cfg_init_n_s <= '0';
    rise_clk(3);
    rise_clk(3);
    cfg_init_n_s <= '1';
    cfg_init_n_s <= '1';
 
 
    -- and receive 32 bytes from set 0
    -- and receive 32 bytes from image 0
    for i in 1 to 32 loop
    for i in 1 to 32 loop
      temp_v := addr_v(0) & calc_crc(addr_v);
      temp_v := addr_v(0) & calc_crc(addr_v);
      read_check_byte(temp_v);
      read_check_byte(temp_v);
      addr_v := addr_v + 1;
      addr_v := addr_v + 1;
    end loop;
    end loop;
    start_s    <= '0';
    start_s    <= '0';
    cfg_done_s <= '1';
    cfg_done_s <= '1';
 
 
    rise_clk(10);
    rise_clk(10);
 
 
    -- request next set
    -- request next image
    mode_s  <= '0';
    mode_s  <= '0';
    start_s <= '1';
    start_s <= '1';
    addr_v  := (others => '0');
    addr_v  := (others => '0');
    addr_v(19 downto 18) := "01"; -- must match num_bits_per_set_g in chip-*-a.vhd
    addr_v(19 downto 18) := "01"; -- must match num_bits_per_img_g in chip-*-a.vhd
    dat_done_s <= '0';
    dat_done_s <= '0';
 
 
    -- receive another 32 bytes from set 1
    -- receive another 32 bytes from image 1
    for i in 1 to 32 loop
    for i in 1 to 32 loop
      temp_v := addr_v(0) & calc_crc(addr_v);
      temp_v := addr_v(0) & calc_crc(addr_v);
      read_check_byte(temp_v);
      read_check_byte(temp_v);
      addr_v := addr_v + 1;
      addr_v := addr_v + 1;
    end loop;
    end loop;
Line 266... Line 266...
    dat_done_s <= '1';
    dat_done_s <= '1';
 
 
 
 
    rise_clk(10);
    rise_clk(10);
 
 
    -- request next set
    -- request next image
    mode_s  <= '1';
    mode_s  <= '1';
    start_s <= '1';
    start_s <= '1';
    addr_v  := (others => '0');
    addr_v  := (others => '0');
    addr_v(19 downto 18) := "10"; -- must match num_bits_per_set_g in chip-*-a.vhd
    addr_v(19 downto 18) := "10"; -- must match num_bits_per_img_g in chip-*-a.vhd
 
 
    wait until config_n_s = '0';
    wait until config_n_s = '0';
    -- run through configuration sequence
    -- run through configuration sequence
    rise_clk(1);
    rise_clk(1);
    cfg_done_s   <= '0';
    cfg_done_s   <= '0';
    cfg_init_n_s <= '0';
    cfg_init_n_s <= '0';
    rise_clk(3);
    rise_clk(3);
    cfg_init_n_s <= '1';
    cfg_init_n_s <= '1';
 
 
    -- receive another 32 bytes from set 2
    -- receive another 32 bytes from image 2
    for i in 1 to 32 loop
    for i in 1 to 32 loop
      temp_v := addr_v(0) & calc_crc(addr_v);
      temp_v := addr_v(0) & calc_crc(addr_v);
      read_check_byte(temp_v);
      read_check_byte(temp_v);
      addr_v := addr_v + 1;
      addr_v := addr_v + 1;
    end loop;
    end loop;
Line 305... Line 305...
 
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File History:
-- File History:
--
--
-- $Log: not supported by cvs2svn $
-- $Log: not supported by cvs2svn $
 
-- Revision 1.3  2005/02/16 19:34:56  arniml
 
-- add weak pull-ups for SPI lines
 
--
-- Revision 1.2  2005/02/13 17:14:03  arniml
-- Revision 1.2  2005/02/13 17:14:03  arniml
-- change dat_done handling
-- change dat_done handling
--
--
-- Revision 1.1  2005/02/08 21:09:20  arniml
-- Revision 1.1  2005/02/08 21:09:20  arniml
-- initial check-in
-- initial check-in

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.