| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- SD/MMC Bootloader
|
-- SD/MMC Bootloader
|
-- Chip toplevel design with minimal feature set
|
-- Chip toplevel design with minimal feature set
|
--
|
--
|
-- $Id: chip-minimal-a.vhd,v 1.1 2005-02-08 20:41:31 arniml Exp $
|
-- $Id: chip-minimal-a.vhd,v 1.2 2005-02-16 18:54:39 arniml Exp $
|
--
|
--
|
-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
|
-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
|
--
|
--
|
-- All rights reserved, see COPYING.
|
-- All rights reserved, see COPYING.
|
--
|
--
|
| Line 65... |
Line 65... |
reset_i : in std_logic;
|
reset_i : in std_logic;
|
spi_clk_o : out std_logic;
|
spi_clk_o : out std_logic;
|
spi_cs_n_o : out std_logic;
|
spi_cs_n_o : out std_logic;
|
spi_data_in_i : in std_logic;
|
spi_data_in_i : in std_logic;
|
spi_data_out_o : out std_logic;
|
spi_data_out_o : out std_logic;
|
|
spi_en_outs_o : out std_logic;
|
start_i : in std_logic;
|
start_i : in std_logic;
|
mode_i : in std_logic;
|
mode_i : in std_logic;
|
config_n_o : out std_logic;
|
config_n_o : out std_logic;
|
cfg_init_n_i : in std_logic;
|
cfg_init_n_i : in std_logic;
|
cfg_done_i : in std_logic;
|
cfg_done_i : in std_logic;
|
| Line 76... |
Line 77... |
cfg_clk_o : out std_logic;
|
cfg_clk_o : out std_logic;
|
cfg_dat_o : out std_logic
|
cfg_dat_o : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
|
signal spi_clk_s : std_logic;
|
|
signal spi_cs_n_s : std_logic;
|
|
signal spi_data_out_s : std_logic;
|
|
signal spi_en_outs_s : std_logic;
|
|
|
begin
|
begin
|
|
|
spi_boot_b : spi_boot
|
spi_boot_b : spi_boot
|
generic map (
|
generic map (
|
width_bit_cnt_g => 6, -- 8 bytes per block
|
width_bit_cnt_g => 6, -- 8 bytes per block
|
| Line 90... |
Line 96... |
width_mmc_clk_div_g => 0 -- no MMC compatibility
|
width_mmc_clk_div_g => 0 -- no MMC compatibility
|
)
|
)
|
port map (
|
port map (
|
clk_i => clk_i,
|
clk_i => clk_i,
|
reset_i => reset_i,
|
reset_i => reset_i,
|
spi_clk_o => spi_clk_o,
|
spi_clk_o => spi_clk_s,
|
spi_cs_n_o => spi_cs_n_o,
|
spi_cs_n_o => spi_cs_n_s,
|
spi_data_in_i => spi_data_in_i,
|
spi_data_in_i => spi_data_in_i,
|
spi_data_out_o => spi_data_out_o,
|
spi_data_out_o => spi_data_out_s,
|
|
spi_en_outs_o => spi_en_outs_s,
|
start_i => start_i,
|
start_i => start_i,
|
mode_i => mode_i,
|
mode_i => mode_i,
|
config_n_o => config_n_o,
|
config_n_o => config_n_o,
|
cfg_init_n_i => cfg_init_n_i,
|
cfg_init_n_i => cfg_init_n_i,
|
cfg_done_i => cfg_done_i,
|
cfg_done_i => cfg_done_i,
|
dat_done_i => dat_done_i,
|
dat_done_i => dat_done_i,
|
cfg_clk_o => cfg_clk_o,
|
cfg_clk_o => cfg_clk_o,
|
cfg_dat_o => cfg_dat_o
|
cfg_dat_o => cfg_dat_o
|
);
|
);
|
|
|
|
-----------------------------------------------------------------------------
|
|
-- Three state drivers for SPI outputs.
|
|
-----------------------------------------------------------------------------
|
|
spi_clk_o <= spi_clk_s
|
|
when spi_en_outs_s = '1' else
|
|
'Z';
|
|
spi_cs_n_o <= spi_cs_n_s
|
|
when spi_en_outs_s = '1' else
|
|
'Z';
|
|
spi_data_out_o <= spi_data_out_s
|
|
when spi_en_outs_s = '1' else
|
|
'Z';
|
|
|
end minimal;
|
end minimal;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.1 2005/02/08 20:41:31 arniml
|
|
-- initial check-in
|
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
No newline at end of file
|
No newline at end of file
|
