| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
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--
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--
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-- SD/MMC Bootloader
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-- SD/MMC Bootloader
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--
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--
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-- $Id: spi_boot.vhd,v 1.2 2005-02-13 17:25:51 arniml Exp $
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-- $Id: spi_boot.vhd,v 1.3 2005-02-16 18:59:10 arniml Exp $
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--
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--
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-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved, see COPYING.
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-- All rights reserved, see COPYING.
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--
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--
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| Line 72... |
Line 72... |
-- Card Interface ---------------------------------------------------------
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-- Card Interface ---------------------------------------------------------
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spi_clk_o : out std_logic;
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spi_clk_o : out std_logic;
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spi_cs_n_o : out std_logic;
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spi_cs_n_o : out std_logic;
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spi_data_in_i : in std_logic;
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spi_data_in_i : in std_logic;
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spi_data_out_o : out std_logic;
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spi_data_out_o : out std_logic;
|
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spi_en_outs_o : out std_logic;
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-- FPGA Configuration Interface -------------------------------------------
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-- FPGA Configuration Interface -------------------------------------------
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start_i : in std_logic;
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start_i : in std_logic;
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mode_i : in std_logic;
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mode_i : in std_logic;
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config_n_o : out std_logic;
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config_n_o : out std_logic;
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cfg_init_n_i : in std_logic;
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cfg_init_n_i : in std_logic;
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| Line 168... |
Line 169... |
|
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signal r1_result_q : std_logic;
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signal r1_result_q : std_logic;
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signal done_q,
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signal done_q,
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send_cmd12_q : boolean;
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send_cmd12_q : boolean;
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|
|
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signal en_outs_s,
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|
en_outs_q : boolean;
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|
|
signal true_s : boolean;
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signal true_s : boolean;
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|
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begin
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begin
|
|
|
true_s <= true;
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true_s <= true;
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| Line 198... |
Line 202... |
done_q <= false;
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done_q <= false;
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send_cmd12_q <= false;
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send_cmd12_q <= false;
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ctrl_fsm_q <= POWER_UP1;
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ctrl_fsm_q <= POWER_UP1;
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cmd_fsm_q <= CMD;
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cmd_fsm_q <= CMD;
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r1_result_q <= '0';
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r1_result_q <= '0';
|
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en_outs_q <= true;
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|
|
elsif clk_i'event and clk_i = '1' then
|
elsif clk_i'event and clk_i = '1' then
|
-- bit counter control
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-- bit counter control
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if spi_clk_rising_q then
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if spi_clk_rising_q then
|
case res_bc_s is
|
case res_bc_s is
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| Line 300... |
Line 305... |
-- an end without interruption or generation of unwanted cfg_clk_q
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-- an end without interruption or generation of unwanted cfg_clk_q
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done_q <= false;
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done_q <= false;
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send_cmd12_q <= false;
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send_cmd12_q <= false;
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end if;
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end if;
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|
|
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-- output enable
|
|
if spi_clk_rising_q then
|
|
en_outs_q <= en_outs_s;
|
|
end if;
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|
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end if;
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end if;
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|
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end process seq;
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end process seq;
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--
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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| Line 449... |
Line 459... |
ctrl_fsm_s <= POWER_UP1;
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ctrl_fsm_s <= POWER_UP1;
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config_n_o <= '1';
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config_n_o <= '1';
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cnt_en_set_s <= false;
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cnt_en_set_s <= false;
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spi_cs_n_s <= '0';
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spi_cs_n_s <= '0';
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mmc_compat_v := false;
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mmc_compat_v := false;
|
|
en_outs_s <= true;
|
|
|
case ctrl_fsm_q is
|
case ctrl_fsm_q is
|
-- Let card finish power up, step 1 -------------------------------------
|
-- Let card finish power up, step 1 -------------------------------------
|
when POWER_UP1 =>
|
when POWER_UP1 =>
|
mmc_compat_v := true;
|
mmc_compat_v := true;
|
| Line 562... |
Line 573... |
ctrl_fsm_s <= CMD18;
|
ctrl_fsm_s <= CMD18;
|
else
|
else
|
ctrl_fsm_s <= WAIT_INIT_LOW;
|
ctrl_fsm_s <= WAIT_INIT_LOW;
|
end if;
|
end if;
|
else
|
else
|
|
en_outs_s <= false;
|
ctrl_fsm_s <= WAIT_START;
|
ctrl_fsm_s <= WAIT_START;
|
end if;
|
end if;
|
else
|
else
|
|
en_outs_s <= false;
|
ctrl_fsm_s <= WAIT_START;
|
ctrl_fsm_s <= WAIT_START;
|
end if;
|
end if;
|
|
|
|
|
-- Wait for INIT to become low ------------------------------------------
|
-- Wait for INIT to become low ------------------------------------------
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| Line 904... |
Line 917... |
-- Output Mapping
|
-- Output Mapping
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
spi_clk_o <= spi_clk_q;
|
spi_clk_o <= spi_clk_q;
|
spi_cs_n_o <= spi_cs_n_q;
|
spi_cs_n_o <= spi_cs_n_q;
|
spi_data_out_o <= spi_dat_q;
|
spi_data_out_o <= spi_dat_q;
|
|
spi_en_outs_o <= '1'
|
|
when en_outs_q else
|
|
'0';
|
cfg_clk_o <= cfg_clk_q;
|
cfg_clk_o <= cfg_clk_q;
|
cfg_dat_o <= cfg_dat_q;
|
cfg_dat_o <= cfg_dat_q;
|
|
|
end rtl;
|
end rtl;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.2 2005/02/13 17:25:51 arniml
|
|
-- major update to fix several problems
|
|
-- configuration/data download of multiple sets works now
|
|
--
|
-- Revision 1.1 2005/02/08 20:41:33 arniml
|
-- Revision 1.1 2005/02/08 20:41:33 arniml
|
-- initial check-in
|
-- initial check-in
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
No newline at end of file
|
No newline at end of file
|
