| Line 111... |
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------------------------------ REVISION HISTORY -----------------------------------------------------------------------
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------------------------------ REVISION HISTORY -----------------------------------------------------------------------
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--
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--
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-- 2011/07/06 v0.01.0010 [JD] started development. verification of synthesis circuit inference.
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-- 2011/07/06 v0.01.0010 [JD] started development. verification of synthesis circuit inference.
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-- 2011/07/07 v1.00.0020 [JD] verification in silicon. operation at 100MHz, tested on the Atlys board (Spartan-6 LX45).
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-- 2011/07/07 v1.00.0020 [JD] verification in silicon. operation at 100MHz, tested on the Atlys board (Spartan-6 LX45).
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-- 2011/08/10 v1.01.0025 [JD] added one pipeline delay to new data strobe output.
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-- 2011/08/10 v1.01.0025 [JD] added one pipeline delay to new data strobe output.
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-- 2011/09/19 v1.01.0030 [JD] changed range for internal counter (cnt_reg, cnt_next) to avoid adder flipover (Altera/ModelSim).
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--
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--
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-----------------------------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------------------------------
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-- TODO
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-- TODO
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-- ====
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-- ====
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--
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--
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signal dat_strb : std_logic := '0'; -- data transfer strobe
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signal dat_strb : std_logic := '0'; -- data transfer strobe
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signal strb_reg : std_logic := '0'; -- registered strobe
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signal strb_reg : std_logic := '0'; -- registered strobe
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signal strb_next : std_logic := '0'; -- lookahead strobe
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signal strb_next : std_logic := '0'; -- lookahead strobe
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signal dat_diff : std_logic := '0'; -- edge detector
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signal dat_diff : std_logic := '0'; -- edge detector
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-- debounce counter
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-- debounce counter
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signal cnt_reg : integer range CNT_VAL downto 0 := 0; -- debounce period counter
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signal cnt_reg : integer range CNT_VAL + 1 downto 0 := 0; -- debounce period counter
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signal cnt_next : integer range CNT_VAL downto 0 := 0; -- combinatorial signal
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signal cnt_next : integer range CNT_VAL + 1 downto 0 := 0; -- combinatorial signal
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begin
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begin
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--=============================================================================================
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--=============================================================================================
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-- DEBOUNCE COUNTER LOGIC
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-- DEBOUNCE COUNTER LOGIC
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--=============================================================================================
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--=============================================================================================
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