URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

Subversion Repositories spi_master_slave

[/] [spi_master_slave/] [trunk/] [syn/] [readme.txt] - Diff between revs 10 and 12

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`The files are:`	`The files are:`
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`spi_master.vhd vhdl model for the spi_master interface`	`spi_master.vhd vhdl model for the spi_master interface`
	`spi_slave.vhd vhdl model for the spi_slave interface`
`grp_debouncer.vhd vhdl model for the switch debouncer`	`grp_debouncer.vhd vhdl model for the switch debouncer`
`spi_master_atlys_top.vhd vhdl model for the toplevel block to synthesize for the Atlys`	`spi_master_atlys_top.vhd vhdl model for the toplevel block to synthesize for the Atlys board`
	`spi_master_atlys_test.vhd testbench for the synthesizable toplevel 'spi_master_atlys_top.vhd'`
`spi_master_atlys.xise ISE 13.1 project file`	`spi_master_atlys.xise ISE 13.1 project file`
`spi_master_atlys.ucf pin lock constraints for the Atlys board`	`spi_master_atlys.ucf pin lock constraints for the Atlys board`
`spi_master_scope_photos.zip Tektronix MSO2014 screenshots for the verification tests`	`spi_master_scope_photos.zip Tektronix MSO2014 screenshots for the verification tests`
`spi_master_envsettings.html synthesis env settings, with the tools setup used`	`spi_master_envsettings.html synthesis env settings, with the tools setup used`
`ATLYS_01.SET Tek MSO2014 settings file with the debug pin names`	`ATLYS_01.SET Tek MSO2014 settings files with the debug pin names`
	`ATLYS_02.SET`
	`ATLYS_03.SET`
`spi_master_atlys_top_bit.zip bitgen file to program the Atlys board`	`spi_master_atlys_top_bit.zip bitgen file to program the Atlys board`



`If you need assistance on putting this to work, please place a thread in the OpenCores forum, and I will be glad to answer.`	`If you need assistance on putting this to work, please place a thread in the OpenCores forum, and I will be glad to answer.`

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Subversion Repositories spi_master_slave

[/] [spi_master_slave/] [trunk/] [syn/] [readme.txt] - Diff between revs 10 and 12