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Line 18... |
spi_master_atlys_test.vhd testbench for the synthesizable toplevel 'spi_master_atlys_top.vhd'
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spi_master_atlys_test.vhd testbench for the synthesizable toplevel 'spi_master_atlys_top.vhd'
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spi_master_atlys.xise ISE 13.1 project file
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spi_master_atlys.xise ISE 13.1 project file
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spi_master_atlys.ucf pin lock constraints for the Atlys board
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spi_master_atlys.ucf pin lock constraints for the Atlys board
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spi_master_scope_photos.zip Tektronix MSO2014 screenshots for the verification tests
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spi_master_scope_photos.zip Tektronix MSO2014 screenshots for the verification tests
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spi_master_envsettings.html synthesis env settings, with the tools setup used
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spi_master_envsettings.html synthesis env settings, with the tools setup used
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ATLYS_01.SET Tek MSO2014 settings files with the debug pin names
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ATLYS_0x.SET Tek MSO2014 settings files with the debug pin names
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ATLYS_02.SET
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ATLYS_03.SET
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spi_master_atlys_top_bit.zip bitgen file to program the Atlys board
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spi_master_atlys_top_bit.zip bitgen file to program the Atlys board
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If you need assistance on putting this to work, please place a thread in the OpenCores forum, and I will be glad to answer.
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If you need assistance on putting this to work, please place a thread in the OpenCores forum, and I will be glad to answer, or send me e-mail: jdoin@opencores.org
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If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at
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If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at
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http://opencores.org/project,spi_master_slave,bugtracker
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http://opencores.org/project,spi_master_slave,bugtracker
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If you find this core useful, please let me know: jdoin@opencores.org
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In any case, thank you very much for testing this core.
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In any case, thank you very much for testing this core.
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Jonny Doin
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Jonny Doin
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jdoin@opencores.org
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jdoin@opencores.org
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