| Line 11... |
Line 11... |
-- This block is the SPI master interface, implemented in one single entity.
|
-- This block is the SPI master interface, implemented in one single entity.
|
-- All internal core operations are synchronous to the 'sclk_i', and a spi base clock is generated by dividing sclk_i downto
|
-- All internal core operations are synchronous to the 'sclk_i', and a spi base clock is generated by dividing sclk_i downto
|
-- a frequency that is 2x the spi SCK line frequency. The divider value is passed as a generic parameter during instantiation.
|
-- a frequency that is 2x the spi SCK line frequency. The divider value is passed as a generic parameter during instantiation.
|
-- All parallel i/o interface operations are synchronous to the 'pclk_i' high speed clock, that can be asynchronous to the serial
|
-- All parallel i/o interface operations are synchronous to the 'pclk_i' high speed clock, that can be asynchronous to the serial
|
-- 'sclk_i' clock.
|
-- 'sclk_i' clock.
|
|
-- For optimized use of longlines, connect 'sclk_i' and 'pclk_i' to the same global clock line.
|
-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two
|
-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two
|
-- clock domains.
|
-- clock domains.
|
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
|
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
|
-- It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), lookahead prefetch signaling
|
-- It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), lookahead prefetch signaling
|
-- ('PREFETCH'), and spi base clock division from sclk_i ('SPI_2X_CLK_DIV').
|
-- ('PREFETCH'), and spi base clock division from sclk_i ('SPI_2X_CLK_DIV').
|
| Line 141... |
Line 142... |
-- 2011/07/24 v1.13.0125 [JD] FIX: 'sck_ena_ce' is on half-cycle advanced to 'fsm_ce', elliminating CPHA='1' glitches.
|
-- 2011/07/24 v1.13.0125 [JD] FIX: 'sck_ena_ce' is on half-cycle advanced to 'fsm_ce', elliminating CPHA='1' glitches.
|
-- Core verified for all CPOL, CPHA at up to 50MHz, simulates to over 100MHz.
|
-- Core verified for all CPOL, CPHA at up to 50MHz, simulates to over 100MHz.
|
-- 2011/07/29 v1.14.0130 [JD] Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
|
-- 2011/07/29 v1.14.0130 [JD] Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
|
-- for each state, to avoid reported inference problems in some synthesis engines.
|
-- for each state, to avoid reported inference problems in some synthesis engines.
|
-- Streamlined port names and indentation blocks.
|
-- Streamlined port names and indentation blocks.
|
|
-- 2011/08/01 v1.15.0135 [JD] Fixed latch inference for spi_mosi_o driver at the fsm.
|
|
-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
|
--
|
--
|
-----------------------------------------------------------------------------------------------------------------------
|
-----------------------------------------------------------------------------------------------------------------------
|
-- TODO
|
-- TODO
|
-- ====
|
-- ====
|
--
|
--
|
| Line 191... |
Line 194... |
sck_ena_o : out std_logic; -- debug: internal sck enable signal
|
sck_ena_o : out std_logic; -- debug: internal sck enable signal
|
sck_ena_ce_o : out std_logic; -- debug: internal sck clock enable signal
|
sck_ena_ce_o : out std_logic; -- debug: internal sck clock enable signal
|
do_transfer_o : out std_logic; -- debug: internal transfer driver
|
do_transfer_o : out std_logic; -- debug: internal transfer driver
|
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
|
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
|
rx_bit_reg_o : out std_logic; -- debug: internal rx bit
|
rx_bit_reg_o : out std_logic; -- debug: internal rx bit
|
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register
|
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
|
core_clk_o : out std_logic;
|
core_clk_o : out std_logic;
|
core_n_clk_o : out std_logic;
|
core_n_clk_o : out std_logic;
|
core_ce_o : out std_logic;
|
core_ce_o : out std_logic;
|
core_n_ce_o : out std_logic;
|
core_n_ce_o : out std_logic;
|
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
|
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
|
| Line 204... |
Line 207... |
|
|
--================================================================================================================
|
--================================================================================================================
|
-- this architecture is a pipelined register-transfer description.
|
-- this architecture is a pipelined register-transfer description.
|
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
|
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
|
--================================================================================================================
|
--================================================================================================================
|
architecture RTL of spi_master is
|
architecture rtl of spi_master is
|
-- core clocks, generated from 'sclk_i': initialized to differential values
|
-- core clocks, generated from 'sclk_i': initialized to differential values
|
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
|
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
|
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
|
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
|
signal core_ce : std_logic := '0'; -- core clock enable, positive logic
|
signal core_ce : std_logic := '0'; -- core clock enable, positive logic
|
signal core_n_ce : std_logic := '1'; -- core clock enable, negative logic
|
signal core_n_ce : std_logic := '1'; -- core clock enable, negative logic
|
| Line 232... |
Line 235... |
--
|
--
|
-- internal state signals for register and combinatorial stages
|
-- internal state signals for register and combinatorial stages
|
signal state_next : natural range N+1 downto 0 := 0;
|
signal state_next : natural range N+1 downto 0 := 0;
|
signal state_reg : natural range N+1 downto 0 := 0;
|
signal state_reg : natural range N+1 downto 0 := 0;
|
-- shifter signals for register and combinatorial stages
|
-- shifter signals for register and combinatorial stages
|
signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0');
|
signal sh_next : std_logic_vector (N-1 downto 0);
|
signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0');
|
signal sh_reg : std_logic_vector (N-1 downto 0);
|
-- input bit sampled buffer
|
-- input bit sampled buffer
|
signal rx_bit_reg : std_logic := '0';
|
signal rx_bit_reg : std_logic := '0';
|
-- buffered di_i data signals for register and combinatorial stages
|
-- buffered di_i data signals for register and combinatorial stages
|
signal di_reg : std_logic_vector (N-1 downto 0) := (others => '0');
|
signal di_reg : std_logic_vector (N-1 downto 0);
|
-- internal wren_i stretcher for fsm combinatorial stage
|
-- internal wren_i stretcher for fsm combinatorial stage
|
signal wren : std_logic := '0';
|
signal wren : std_logic;
|
signal wr_ack_next : std_logic := '0';
|
signal wr_ack_next : std_logic := '0';
|
signal wr_ack_reg : std_logic := '0';
|
signal wr_ack_reg : std_logic := '0';
|
-- internal SSEL enable control signals
|
-- internal SSEL enable control signals
|
signal ssel_ena_next : std_logic := '0';
|
signal ssel_ena_next : std_logic := '0';
|
signal ssel_ena_reg : std_logic := '0';
|
signal ssel_ena_reg : std_logic := '0';
|
-- internal SCK enable control signals
|
-- internal SCK enable control signals
|
signal sck_ena_next : std_logic;
|
signal sck_ena_next : std_logic;
|
signal sck_ena_reg : std_logic;
|
signal sck_ena_reg : std_logic;
|
-- buffered do_o data signals for register and combinatorial stages
|
-- buffered do_o data signals for register and combinatorial stages
|
signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0');
|
signal do_buffer_next : std_logic_vector (N-1 downto 0);
|
signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0');
|
signal do_buffer_reg : std_logic_vector (N-1 downto 0);
|
-- internal signal to flag transfer to do_buffer_reg
|
-- internal signal to flag transfer to do_buffer_reg
|
signal do_transfer_next : std_logic := '0';
|
signal do_transfer_next : std_logic := '0';
|
signal do_transfer_reg : std_logic := '0';
|
signal do_transfer_reg : std_logic := '0';
|
-- internal input data request signal
|
-- internal input data request signal
|
signal di_req_next : std_logic := '0';
|
signal di_req_next : std_logic := '0';
|
| Line 307... |
Line 310... |
-- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock
|
-- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock
|
-- enables are used to control clocking of all internal synchronous circuitry.
|
-- enables are used to control clocking of all internal synchronous circuitry.
|
-- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output,
|
-- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output,
|
-- based on the configuration of CPOL and CPHA.
|
-- based on the configuration of CPOL and CPHA.
|
-- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
|
-- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
|
-- modes, by a single high-speed global clock, preserving clock resources.
|
-- modes, by a single high-speed global clock, preserving clock resources and clock to data skew.
|
-----------------------------------------------------------------------------------------------
|
-----------------------------------------------------------------------------------------------
|
-- generate the 2x spi base clock enable from the serial high-speed input clock
|
-- generate the 2x spi base clock enable from the serial high-speed input clock
|
spi_2x_ce_gen_proc: process (sclk_i) is
|
spi_2x_ce_gen_proc: process (sclk_i) is
|
variable clk_cnt : integer range SPI_2X_CLK_DIV-1 downto 0 := 0;
|
variable clk_cnt : integer range SPI_2X_CLK_DIV-1 downto 0 := 0;
|
begin
|
begin
|
| Line 355... |
Line 358... |
|
|
spi_sck_cpol_1_proc: if CPOL = '1' generate
|
spi_sck_cpol_1_proc: if CPOL = '1' generate
|
begin
|
begin
|
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH
|
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH
|
end generate;
|
end generate;
|
|
|
-----------------------------------------------------------------------------------------------
|
-----------------------------------------------------------------------------------------------
|
-- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
|
-- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
|
-- always sample data at the half-cycle of the fsm update cell
|
-- always sample data at the half-cycle of the fsm update cell
|
samp_ce_cpha_0_proc: if CPHA = '0' generate
|
samp_ce_cpha_0_proc: if CPHA = '0' generate
|
begin
|
begin
|
| Line 379... |
Line 381... |
|
|
fsm_ce_cpha_1_proc: if CPHA = '1' generate
|
fsm_ce_cpha_1_proc: if CPHA = '1' generate
|
begin
|
begin
|
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable
|
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable
|
end generate;
|
end generate;
|
|
-----------------------------------------------------------------------------------------------
|
|
-- sck enable control: control sck advance phase for CPHA='1' relative to fsm clock
|
sck_ena_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle
|
sck_ena_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle
|
|
|
--=============================================================================================
|
--=============================================================================================
|
-- REGISTERED INPUTS
|
-- REGISTERED INPUTS
|
--=============================================================================================
|
--=============================================================================================
|
-- rx bit flop: capture rx bit after SAMPLE edge of sck
|
-- rx bit flop: capture rx bit after SAMPLE edge of sck
|
--
|
|
-- ATTENTION: REMOVING THE FLIPFLOP (DIRECT CONNECTION) WE GET HIGHER PERFORMANCE DUE TO
|
|
-- REDUCED DEMAND ON MISO SETUP TIME.
|
|
--
|
|
rx_bit_proc : process (sclk_i, spi_miso_i) is
|
rx_bit_proc : process (sclk_i, spi_miso_i) is
|
begin
|
begin
|
if sclk_i'event and sclk_i = '1' then
|
if sclk_i'event and sclk_i = '1' then
|
if samp_ce = '1' then
|
if samp_ce = '1' then
|
rx_bit_reg <= spi_miso_i;
|
rx_bit_reg <= spi_miso_i;
|
| Line 448... |
Line 447... |
end if;
|
end if;
|
end if;
|
end if;
|
end process in_transfer_proc;
|
end process in_transfer_proc;
|
|
|
--=============================================================================================
|
--=============================================================================================
|
-- RTL REGISTER PROCESSES
|
-- REGISTER TRANSFER PROCESSES
|
--=============================================================================================
|
--=============================================================================================
|
-- fsm state and data registers: synchronous to the spi base reference clock
|
-- fsm state and data registers: synchronous to the spi base reference clock
|
core_reg_proc : process (sclk_i) is
|
core_reg_proc : process (sclk_i) is
|
begin
|
begin
|
-- FF registers clocked on rising edge and cleared on sync rst_i
|
-- FF registers clocked on rising edge and cleared on sync rst_i
|
| Line 481... |
Line 480... |
end if;
|
end if;
|
end if;
|
end if;
|
end process core_reg_proc;
|
end process core_reg_proc;
|
|
|
--=============================================================================================
|
--=============================================================================================
|
-- RTL combinatorial LOGIC PROCESSES
|
-- COMBINATORIAL LOGIC PROCESSES
|
--=============================================================================================
|
--=============================================================================================
|
-- state and datapath combinatorial logic
|
-- state and datapath combinatorial logic
|
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg,
|
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg,
|
do_transfer_reg, wr_ack_reg, di_req_reg, di_reg, wren ) is
|
do_transfer_reg, wr_ack_reg, di_req_reg, di_reg, wren ) is
|
begin
|
begin
|
| Line 494... |
Line 493... |
sck_ena_next <= sck_ena_reg; -- controls the clock enable of spi sck line
|
sck_ena_next <= sck_ena_reg; -- controls the clock enable of spi sck line
|
do_buffer_next <= do_buffer_reg; -- output data buffer
|
do_buffer_next <= do_buffer_reg; -- output data buffer
|
do_transfer_next <= do_transfer_reg; -- output data flag
|
do_transfer_next <= do_transfer_reg; -- output data flag
|
wr_ack_next <= wr_ack_reg; -- write acknowledge
|
wr_ack_next <= wr_ack_reg; -- write acknowledge
|
di_req_next <= di_req_reg; -- prefetch data request
|
di_req_next <= di_req_reg; -- prefetch data request
|
|
spi_mosi_o <= sh_reg(N-1); -- default to avoid latch inference
|
state_next <= state_reg; -- next state
|
state_next <= state_reg; -- next state
|
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
|
|
case state_reg is
|
case state_reg is
|
when (N+1) => -- this state is to enable SSEL before SCK
|
when (N+1) => -- this state is to enable SSEL before SCK
|
|
-- slave select
|
|
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
|
ssel_ena_next <= '1'; -- tx in progress: will assert SSEL
|
ssel_ena_next <= '1'; -- tx in progress: will assert SSEL
|
sck_ena_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle)
|
sck_ena_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle)
|
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
|
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
|
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
|
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
|
state_next <= state_reg - 1; -- update next state at each sck pulse
|
state_next <= state_reg - 1; -- update next state at each sck pulse
|
when (N) => -- deassert 'di_rdy'
|
when (N) => -- deassert 'di_rdy'
|
|
-- stretch do_valid
|
|
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
|
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
|
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
|
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
|
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
|
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
|
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
|
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
|
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
|
state_next <= state_reg - 1; -- update next state at each sck pulse
|
state_next <= state_reg - 1; -- update next state at each sck pulse
|
when (N-1) downto (PREFETCH+3) => -- if rx data is valid, raise 'do_valid'. remove 'do_transfer'
|
when (N-1) downto (PREFETCH+3) => -- if rx data is valid, raise 'do_valid'. remove 'do_transfer'
|
|
-- send bit out and shif bit in
|
|
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
|
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
|
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
|
do_transfer_next <= '0'; -- reset transfer signal
|
do_transfer_next <= '0'; -- reset transfer signal
|
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
|
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
|
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
|
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
|
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
|
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
|
state_next <= state_reg - 1; -- update next state at each sck pulse
|
state_next <= state_reg - 1; -- update next state at each sck pulse
|
when (PREFETCH+2) downto 2 => -- raise prefetch 'di_req_o_next' signal and remove 'do_valid'
|
when (PREFETCH+2) downto 2 => -- raise prefetch 'di_req_o_next' signal and remove 'do_valid'
|
|
-- raise data prefetch request
|
|
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
|
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
|
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
|
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
|
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
|
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
|
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
|
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
|
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
|
state_next <= state_reg - 1; -- update next state at each sck pulse
|
state_next <= state_reg - 1; -- update next state at each sck pulse
|
when 1 => -- transfer rx data to do_buffer and restart if wren
|
when 1 => -- transfer rx data to do_buffer and restart if wren
|
|
-- load next word or end transmission
|
|
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
|
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
|
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
|
do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer
|
do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer
|
do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer
|
do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer
|
do_transfer_next <= '1'; -- signal transfer to do_buffer
|
do_transfer_next <= '1'; -- signal transfer to do_buffer
|
if wren = '1' then -- load tx register if valid data present at di_i
|
if wren = '1' then -- load tx register if valid data present at di_i
|
| Line 538... |
Line 547... |
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
|
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
|
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
|
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
|
state_next <= state_reg - 1; -- update next state at each sck pulse
|
state_next <= state_reg - 1; -- update next state at each sck pulse
|
end if;
|
end if;
|
when 0 =>
|
when 0 =>
|
|
-- idle state: start and end of transmission
|
di_req_next <= '1'; -- will request data if shifter empty
|
di_req_next <= '1'; -- will request data if shifter empty
|
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
|
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
|
if wren = '1' then -- load tx register if valid data present at di_i
|
if wren = '1' then -- load tx register if valid data present at di_i
|
|
spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead)
|
ssel_ena_next <= '1'; -- enable interface SSEL
|
ssel_ena_next <= '1'; -- enable interface SSEL
|
state_next <= N+1; -- start from idle: let one cycle for SSEL settling
|
state_next <= N+1; -- start from idle: let one cycle for SSEL settling
|
spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead)
|
|
sh_next <= di_reg; -- load bits from di_reg into shifter
|
sh_next <= di_reg; -- load bits from di_reg into shifter
|
wr_ack_next <= '1'; -- acknowledge data in transfer
|
wr_ack_next <= '1'; -- acknowledge data in transfer
|
else
|
else
|
|
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
|
ssel_ena_next <= '0'; -- deassert SSEL: interface is idle
|
ssel_ena_next <= '0'; -- deassert SSEL: interface is idle
|
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
|
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
|
state_next <= 0; -- when idle, keep this state
|
state_next <= 0; -- when idle, keep this state
|
end if;
|
end if;
|
when others =>
|
when others =>
|
| Line 586... |
Line 597... |
end process spi_sck_o_gen_proc;
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end process spi_sck_o_gen_proc;
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--=============================================================================================
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--=============================================================================================
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-- DEBUG LOGIC PROCESSES
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-- DEBUG LOGIC PROCESSES
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--=============================================================================================
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--=============================================================================================
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-- these signals are useful for verification, and can be deleted or commented-out after debug.
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-- these signals are useful for verification, and can be deleted after debug.
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do_transfer_proc: do_transfer_o <= do_transfer_reg;
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do_transfer_proc: do_transfer_o <= do_transfer_reg;
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state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6));
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state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4));
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rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg;
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rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg;
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wren_o_proc: wren_o <= wren;
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wren_o_proc: wren_o <= wren;
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sh_reg_dbg_proc: sh_reg_dbg_o <= sh_reg;
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sh_reg_dbg_proc: sh_reg_dbg_o <= sh_reg;
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core_clk_o_proc: core_clk_o <= core_clk;
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core_clk_o_proc: core_clk_o <= core_clk;
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core_n_clk_o_proc: core_n_clk_o <= core_n_clk;
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core_n_clk_o_proc: core_n_clk_o <= core_n_clk;
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core_ce_o_proc: core_ce_o <= core_ce;
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core_ce_o_proc: core_ce_o <= core_ce;
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core_n_ce_o_proc: core_n_ce_o <= core_n_ce;
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core_n_ce_o_proc: core_n_ce_o <= core_n_ce;
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sck_ena_o_proc: sck_ena_o <= sck_ena_reg;
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sck_ena_o_proc: sck_ena_o <= sck_ena_reg;
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sck_ena_ce_o_proc: sck_ena_ce_o <= sck_ena_ce;
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sck_ena_ce_o_proc: sck_ena_ce_o <= sck_ena_ce;
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end architecture RTL;
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end architecture rtl;
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