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-- There are several output ports that are used to simulate and verify the core operation.
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-- There are several output ports that are used to simulate and verify the core operation.
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-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
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-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
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-- circuitry.
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-- circuitry.
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-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
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-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
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-- synthesis tool will remove the receive logic from the generated circuitry.
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-- synthesis tool will remove the receive logic from the generated circuitry.
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-- Alternatively, you can remove these ports and related circuitry once the core is verified and
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-- integrated to your circuit.
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--================================================================================================================
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--================================================================================================================
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entity spi_master is
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entity spi_master is
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Generic (
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Generic (
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N : positive := 32; -- 32bit serial word length is default
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N : positive := 32; -- 32bit serial word length is default
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--================================================================================================================
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--================================================================================================================
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-- this architecture is a pipelined register-transfer description.
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-- this architecture is a pipelined register-transfer description.
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-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
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-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
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--================================================================================================================
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--================================================================================================================
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architecture rtl of spi_master is
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architecture rtl of spi_master is
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-- core clocks, generated from 'sclk_i': initialized to differential values
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-- core clocks, generated from 'sclk_i': initialized at GSR to differential values
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signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
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signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
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signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
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signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
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signal core_ce : std_logic := '0'; -- core clock enable, positive logic
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signal core_ce : std_logic := '0'; -- core clock enable, positive logic
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signal core_n_ce : std_logic := '1'; -- core clock enable, negative logic
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signal core_n_ce : std_logic := '1'; -- core clock enable, negative logic
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-- spi bus clock, generated from the CPOL selected core clock polarity
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-- spi bus clock, generated from the CPOL selected core clock polarity
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-- CLOCK GENERATION
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-- CLOCK GENERATION
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--=============================================================================================
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--=============================================================================================
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-- In order to preserve global clocking resources, the core clocking scheme is completely based
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-- In order to preserve global clocking resources, the core clocking scheme is completely based
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-- on using clock enables to process the serial high-speed clock at lower rates for the core fsm,
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-- on using clock enables to process the serial high-speed clock at lower rates for the core fsm,
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-- the spi clock generator and the input sampling clock.
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-- the spi clock generator and the input sampling clock.
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-- The clock generation block derive 2 continuous antiphase signals from the 2x spi base clock
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-- The clock generation block derives 2 continuous antiphase signals from the 2x spi base clock
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-- for the core clocking.
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-- for the core clocking.
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-- The 2 clock phases are generated by separate and synchronous FFs, and should have only
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-- The 2 clock phases are generated by separate and synchronous FFs, and should have only
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-- differential interconnect delay skew.
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-- differential interconnect delay skew.
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-- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock
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-- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock
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-- enables are used to control clocking of all internal synchronous circuitry.
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-- enables are used to control clocking of all internal synchronous circuitry.
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