| Line 117... |
Line 117... |
-- Streamlined port names and indentation blocks.
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-- Streamlined port names and indentation blocks.
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-- 2011/08/01 v2.01.0115 [JD] Adjusted 'do_valid_o' pulse width to be 2 'clk_i', as in the master core.
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-- 2011/08/01 v2.01.0115 [JD] Adjusted 'do_valid_o' pulse width to be 2 'clk_i', as in the master core.
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-- Simulated in iSim with the master core for continuous transmission mode.
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-- Simulated in iSim with the master core for continuous transmission mode.
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-- 2011/08/02 v2.02.0120 [JD] Added mux for MISO at reset state, to output di(N-1) at start. This fixed a bug in first bit.
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-- 2011/08/02 v2.02.0120 [JD] Added mux for MISO at reset state, to output di(N-1) at start. This fixed a bug in first bit.
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-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
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-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
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-- 2011/08/04 v2.02.0121 [JD] Changed minor comment bugs in the combinatorial fsm logic.
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--
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--
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--
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--
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-----------------------------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------------------------------
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-- TODO
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-- TODO
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-- ====
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-- ====
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| Line 334... |
Line 335... |
wr_ack_next <= wr_ack_reg; -- write enable acknowledge
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wr_ack_next <= wr_ack_reg; -- write enable acknowledge
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di_req_next <= di_req_reg; -- data input request
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di_req_next <= di_req_reg; -- data input request
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state_next <= state_reg; -- fsm control state
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state_next <= state_reg; -- fsm control state
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case state_reg is
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case state_reg is
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when (N) =>
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when (N) => -- deassert 'di_rdy' and stretch do_valid
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-- stretch do_valid
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wr_ack_next <= '0'; -- acknowledge data in transfer
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wr_ack_next <= '0'; -- acknowledge data in transfer
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di_req_next <= '0'; -- prefetch data request: deassert when shifting data
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di_req_next <= '0'; -- prefetch data request: deassert when shifting data
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tx_bit_next <= sh_reg(N-1); -- output next MSbit
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tx_bit_next <= sh_reg(N-1); -- output next MSbit
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sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
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sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
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sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
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sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
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state_next <= state_reg - 1; -- update next state at each sck pulse
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state_next <= state_reg - 1; -- update next state at each sck pulse
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when (N-1) downto (PREFETCH+3) =>
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when (N-1) downto (PREFETCH+3) => -- remove 'do_transfer' and shift bits
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-- send bit out and shif bit in
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do_transfer_next <= '0'; -- reset 'do_valid' transfer signal
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do_transfer_next <= '0'; -- reset transfer signal
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di_req_next <= '0'; -- prefetch data request: deassert when shifting data
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di_req_next <= '0'; -- prefetch data request: deassert when shifting data
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wr_ack_next <= '0'; -- remove data load ack for all but the load stages
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wr_ack_next <= '0'; -- remove data load ack for all but the load stages
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tx_bit_next <= sh_reg(N-1); -- output next MSbit
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tx_bit_next <= sh_reg(N-1); -- output next MSbit
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sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
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sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
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sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
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sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
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state_next <= state_reg - 1; -- update next state at each sck pulse
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state_next <= state_reg - 1; -- update next state at each sck pulse
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when (PREFETCH+2) downto 3 =>
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when (PREFETCH+2) downto 3 => -- raise prefetch 'di_req_o' signal
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-- raise data prefetch request
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di_req_next <= '1'; -- request data in advance to allow for pipeline delays
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di_req_next <= '1'; -- request data in advance to allow for pipeline delays
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wr_ack_next <= '0'; -- remove data load ack for all but the load stages
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wr_ack_next <= '0'; -- remove data load ack for all but the load stages
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tx_bit_next <= sh_reg(N-1); -- output next MSbit
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tx_bit_next <= sh_reg(N-1); -- output next MSbit
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sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
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sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
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sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
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sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
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state_next <= state_reg - 1; -- update next state at each sck pulse
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state_next <= state_reg - 1; -- update next state at each sck pulse
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when 2 =>
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when 2 => -- transfer received data to do_buffer_reg on next cycle
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-- transfer parallel data on next state
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di_req_next <= '1'; -- request data in advance to allow for pipeline delays
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di_req_next <= '1'; -- request data in advance to allow for pipeline delays
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wr_ack_next <= '0'; -- remove data load ack for all but the load stages
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wr_ack_next <= '0'; -- remove data load ack for all but the load stages
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tx_bit_next <= sh_reg(N-1); -- output next MSbit
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tx_bit_next <= sh_reg(N-1); -- output next MSbit
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sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
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sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
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sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
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sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
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do_transfer_next <= '1'; -- signal transfer to do_buffer on next cycle
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do_transfer_next <= '1'; -- signal transfer to do_buffer on next cycle
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do_buffer_next <= sh_next; -- get next data directly into rx buffer
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do_buffer_next <= sh_next; -- get next data directly into rx buffer
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state_next <= state_reg - 1; -- update next state at each sck pulse
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state_next <= state_reg - 1; -- update next state at each sck pulse
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when 1 =>
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when 1 => -- transfer rx data to do_buffer and restart if new data is written
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-- restart from state 'N' if more sck pulses come
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sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
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sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
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sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
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sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
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tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data
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tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data
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di_req_next <= '0'; -- prefetch data request: deassert when shifting data
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di_req_next <= '0'; -- prefetch data request: deassert when shifting data
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if wren = '1' then -- load tx register if valid data present at di_reg
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if wren = '1' then -- load tx register if valid data present at di_reg
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| Line 388... |
Line 384... |
wr_ack_next <= '0'; -- remove data load ack for all but the load stages
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wr_ack_next <= '0'; -- remove data load ack for all but the load stages
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sh_next <= (others => '0'); -- load null data (output '0' if no load)
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sh_next <= (others => '0'); -- load null data (output '0' if no load)
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state_next <= 0; -- next state is idle state
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state_next <= 0; -- next state is idle state
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end if;
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end if;
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when 0 =>
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when 0 => -- idle state: start and end of transmission
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sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
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sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
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sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
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sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
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wr_ack_next <= '1'; -- acknowledge data in transfer
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wr_ack_next <= '1'; -- acknowledge data in transfer
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di_req_next <= '0'; -- prefetch data request: deassert when shifting data
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di_req_next <= '0'; -- prefetch data request: deassert when shifting data
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do_transfer_next <= '0'; -- clear signal transfer to do_buffer
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do_transfer_next <= '0'; -- clear signal transfer to do_buffer
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