| Line 4... |
Line 4... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : opb_spi_slave_tb.vhd
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-- File : opb_spi_slave_tb.vhd
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-- Author :
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-- Author :
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-- Company :
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-- Company :
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-- Created : 2007-09-02
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-- Created : 2007-09-02
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-- Last update: 2007-11-18
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-- Last update: 2007-12-03
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-- Platform :
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-- Platform :
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-- Standard : VHDL'87
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-- Standard : VHDL'87
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description:
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-- Description:
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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| Line 27... |
Line 27... |
library work;
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library work;
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use work.opb_spi_slave_pack.all;
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use work.opb_spi_slave_pack.all;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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entity opb_spi_slave_tb is
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entity opb_spi_slave_tb is
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generic (
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-- 0: simple transfer 1 byte transmit/receive
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-- 1: transfer 4 bytes and check flags
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-- 2: write until TX-FIFO asserts full, read until RX-FIFO asserts full, read
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-- and compare data
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-- 3: check FIFO Reset form underflow condition
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-- 4: check FIFO Flags IRQ Generation
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-- 5: check Slave select IRQ Generation
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-- 6: test opb Master Transfer
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test : std_logic_vector(7 downto 0) := "11111111");
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end opb_spi_slave_tb;
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end opb_spi_slave_tb;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture behavior of opb_spi_slave_tb is
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architecture behavior of opb_spi_slave_tb is
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| Line 142... |
Line 151... |
signal miso : std_logic;
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signal miso : std_logic;
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signal opb_read_data : std_logic_vector(31 downto 0);
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signal opb_read_data : std_logic_vector(31 downto 0);
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signal spi_value_in : std_logic_vector(C_SR_WIDTH-1 downto 0);
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signal spi_value_in : std_logic_vector(C_SR_WIDTH-1 downto 0);
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signal OPB_Transfer_Abort : boolean;
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begin -- behavior
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begin -- behavior
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-- component instantiation
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-- component instantiation
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DUT : opb_spi_slave
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DUT : opb_spi_slave
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generic map (
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generic map (
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| Line 216... |
Line 227... |
process(OPB_Rst, OPB_Clk)
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process(OPB_Rst, OPB_Clk)
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begin
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begin
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if (OPB_Rst = '1') then
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if (OPB_Rst = '1') then
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MOPB_MGrant <= '0';
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MOPB_MGrant <= '0';
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MOPB_xferAck <= '0';
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MOPB_xferAck <= '0';
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MOPB_errAck <= '0';
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elsif rising_edge(OPB_Clk) then
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elsif rising_edge(OPB_Clk) then
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-- arbiter
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-- arbiter
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if (M_request = '1') then
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if (M_request = '1') then
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MOPB_MGrant <= '1';
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MOPB_MGrant <= '1';
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else
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else
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MOPB_MGrant <= '0';
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MOPB_MGrant <= '0';
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end if;
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end if;
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-- xfer_Ack
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-- xfer_Ack
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if (M_select = '1') then
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if (M_select = '1') then
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if (OPB_Transfer_Abort) then
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MOPB_errAck <= '1';
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else
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MOPB_xferAck <= not MOPB_xferAck;
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MOPB_xferAck <= not MOPB_xferAck;
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end if;
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else
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else
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MOPB_errAck <= '0';
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MOPB_xferAck <= '0';
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MOPB_xferAck <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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| Line 320... |
Line 339... |
OPB_RNW <= '0';
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OPB_RNW <= '0';
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OPB_select <= '0';
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OPB_select <= '0';
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OPB_seqAddr <= '0';
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OPB_seqAddr <= '0';
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-- int opb_master
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-- int opb_master
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MOPB_errAck <= '0';
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MOPB_retry <= '0';
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MOPB_retry <= '0';
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MOPB_timeout <= '0';
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MOPB_timeout <= '0';
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OPB_Transfer_Abort <= false;
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-- reset active
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-- reset active
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OPB_Rst <= '1';
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OPB_Rst <= '1';
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wait for 100 ns;
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wait for 100 ns;
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-- reset inactive
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-- reset inactive
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OPB_Rst <= '0';
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OPB_Rst <= '0';
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| Line 348... |
Line 368... |
opb_write(C_ADR_RX_THRESH, 16#0006000C#);
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opb_write(C_ADR_RX_THRESH, 16#0006000C#);
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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-- simple transfer 1 byte transmit/receive
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-- simple transfer 1 byte transmit/receive
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if (test(0) = '1') then
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-- write transmit data
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-- write transmit data
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opb_write(C_ADR_TX_DATA, 16#78#);
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opb_write(C_ADR_TX_DATA, 16#78#);
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-- enable GDE and TX_EN and RX_EN
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-- enable GDE and TX_EN and RX_EN
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opb_write(C_ADR_CTL, 16#7#);
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opb_write(C_ADR_CTL, 16#7#);
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| Line 367... |
Line 387... |
opb_read(C_ADR_RX_DATA);
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opb_read(C_ADR_RX_DATA);
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-- compare receive data
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-- compare receive data
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assert (opb_read_data = conv_std_logic_vector(16#B5#,C_SR_WIDTH)) report "Master Transfer Failure" severity failure;
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assert (opb_read_data = conv_std_logic_vector(16#B5#,C_SR_WIDTH)) report "Master Transfer Failure" severity failure;
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end if;
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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-- transfer 4 bytes and check flags
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-- transfer 4 bytes and check flags
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if (test(1) = '1') then
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opb_read(C_ADR_STATUS);
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opb_read(C_ADR_STATUS);
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-- only empty Bit and prog_empty set
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-- only empty Bit and prog_empty set
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temp := (others => '0');
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temp := (others => '0');
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temp(SPI_SR_Bit_TX_Prog_empty) := '1';
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temp(SPI_SR_Bit_TX_Prog_empty) := '1';
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| Line 393... |
Line 415... |
temp(SPI_SR_Bit_RX_Prog_empty) := '1';
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temp(SPI_SR_Bit_RX_Prog_empty) := '1';
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temp(SPI_SR_Bit_RX_Empty) := '1';
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temp(SPI_SR_Bit_RX_Empty) := '1';
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temp(SPI_SR_Bit_SS_n) := '1';
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temp(SPI_SR_Bit_SS_n) := '1';
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assert (opb_read_data = temp) report "Check Status Bits: TX: 1, RX:0" severity failure;
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assert (opb_read_data = temp) report "Check Status Bits: TX: 1, RX:0" severity failure;
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end if;
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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-- write until TX-FIFO asserts full, read until RX-FIFO asserts full, read an
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-- compare data
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if (test(2) = '1') then
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for i in 2 to 255 loop
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for i in 2 to 255 loop
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opb_write(C_ADR_TX_DATA, i);
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opb_write(C_ADR_TX_DATA, i);
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opb_read(C_ADR_STATUS);
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opb_read(C_ADR_STATUS);
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-- check TX prog_empty deassert
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-- check TX prog_empty deassert
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if ((opb_read_data(SPI_SR_Bit_TX_Prog_empty) = '0') and first(0) = '0') then
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if ((opb_read_data(SPI_SR_Bit_TX_Prog_empty) = '0') and first(0) = '0') then
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| Line 481... |
Line 506... |
first(7) := '1';
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first(7) := '1';
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exit;
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exit;
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end if;
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end if;
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end loop; -- i
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end loop; -- i
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|
|
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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-- read data from fifo
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-- read data from fifo
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first := (others => '0');
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first := (others => '0');
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for i in 1 to 255 loop
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for i in 1 to 255 loop
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| Line 520... |
Line 546... |
assert (false) report "RX empty assert after " & integer'image(i) & " transfers." severity warning;
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assert (false) report "RX empty assert after " & integer'image(i) & " transfers." severity warning;
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first(3) := '1';
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first(3) := '1';
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exit;
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exit;
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end if;
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end if;
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end loop; -- i
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end loop; -- i
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end if;
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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-- check FIFO Reset form underflow condition
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if (test(3) = '1') then
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-- add transfer to go in underflow condition
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-- add transfer to go in underflow condition
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spi_transfer(conv_std_logic_vector(0, C_SR_WIDTH));
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spi_transfer(conv_std_logic_vector(0, C_SR_WIDTH));
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-- reset core (Bit 4)
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-- reset core (Bit 4)
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opb_write(C_ADR_CTL, 16#F#);
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opb_write(C_ADR_CTL, 16#F#);
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| Line 538... |
Line 566... |
temp(SPI_SR_Bit_RX_Prog_empty) := '1';
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temp(SPI_SR_Bit_RX_Prog_empty) := '1';
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temp(SPI_SR_Bit_RX_Empty) := '1';
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temp(SPI_SR_Bit_RX_Empty) := '1';
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temp(SPI_SR_Bit_SS_n) := '1';
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temp(SPI_SR_Bit_SS_n) := '1';
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assert (opb_read_data = temp) report "Status Bits after Reset failure" severity failure;
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assert (opb_read_data = temp) report "Status Bits after Reset failure" severity failure;
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end if;
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-------------------------------------------------------------------------------
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-- check FIFO Flags IRQ Generation
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if (test(4) = '1') then
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-- enable all IRQ except Chip select
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-- enable all IRQ except Chip select
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opb_write(C_ADR_IER, 16#3F#);
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opb_write(C_ADR_IER, 16#3F#);
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-- global irq enable
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-- global irq enable
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opb_write(C_ADR_DGIE, 16#1#);
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opb_write(C_ADR_DGIE, 16#1#);
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| Line 621... |
Line 652... |
end if;
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end if;
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|
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end if;
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end if;
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end loop; -- i
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end loop; -- i
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end if;
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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-- check Chip select irq
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-- check slave select irq
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if (test(5) = '1') then
|
-- reset core
|
-- reset core
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opb_write(C_ADR_CTL, 16#F#);
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opb_write(C_ADR_CTL, 16#F#);
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-- eable Chip select fall/rise IRQ
|
-- eable Chip select fall/rise IRQ
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opb_write(C_ADR_IER, 16#C0#);
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opb_write(C_ADR_IER, 16#C0#);
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| Line 659... |
Line 691... |
opb_write(C_ADR_ISR, 2**SPI_ISR_Bit_SS_Rise);
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opb_write(C_ADR_ISR, 2**SPI_ISR_Bit_SS_Rise);
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wait until rising_edge(OPB_Clk);
|
wait until rising_edge(OPB_Clk);
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assert (opb_irq = '0') report "SS_Rise IRQ not cleared" severity warning;
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assert (opb_irq = '0') report "SS_Rise IRQ not cleared" severity warning;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
end if;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- test opb Master Transfer
|
-- test opb Master Transfer
|
|
if (test(6) = '1') then
|
-- write TX Threshold
|
-- write TX Threshold
|
-- Bit [15:00] Prog Full Threshold
|
-- Bit [15:00] Prog Full Threshold
|
-- Bit [31:16] Prog Empty Threshold
|
-- Bit [31:16] Prog Empty Threshold
|
opb_write(C_ADR_TX_THRESH, 16#0005000B#);
|
opb_write(C_ADR_TX_THRESH, 16#0005000B#);
|
|
|
| Line 708... |
Line 742... |
opb_write(C_ADR_RX_DMA_CTL, 16#1#);
|
opb_write(C_ADR_RX_DMA_CTL, 16#1#);
|
|
|
-- emulate DDR-Memory Controller
|
-- emulate DDR-Memory Controller
|
wait until M_select = '1';
|
wait until M_select = '1';
|
for i in 0 to 15 loop
|
for i in 0 to 15 loop
|
|
if (i = 15) then
|
|
OPB_Transfer_Abort <= true;
|
|
wait until falling_edge(MOPB_errAck);
|
|
OPB_Transfer_Abort <= false;
|
|
exit;
|
|
end if;
|
wait until falling_edge(MOPB_xferAck);
|
wait until falling_edge(MOPB_xferAck);
|
assert (conv_integer(M_ABus) = 16#25000000#+i*4) report "DMA transfer 1 write adr failure" severity failure;
|
assert (conv_integer(M_ABus) = 16#25000000#+i*4) report "DMA transfer 1 write adr failure" severity failure;
|
assert (conv_integer(M_DBus) = i) report "DMA transfer 1 write data failure" severity failure;
|
assert (conv_integer(M_DBus) = i) report "DMA transfer 1 write data failure" severity failure;
|
end loop; -- i
|
end loop; -- i
|
|
|
|
|
|
|
-- transfer second 16 bytes
|
-- transfer second 16 bytes
|
for i in 16 to 31 loop
|
for i in 16 to 31 loop
|
spi_transfer(conv_std_logic_vector(i, C_SR_WIDTH));
|
spi_transfer(conv_std_logic_vector(i, C_SR_WIDTH));
|
-- disabled because simultaneous controller emulation and SPI Transfer impossible
|
-- disabled because simultaneous controller emulation and SPI Transfer impossible
|
-- assert (conv_integer(spi_value_in) = i) report "DMA Transfer 2 read data failure" severity failure;
|
-- assert (conv_integer(spi_value_in) = i) report "DMA Transfer 2 read data failure" severity failure;
|
end loop; -- i
|
end loop; -- i
|
|
|
|
|
wait for 1 us;
|
wait for 1 us;
|
|
end if;
|
|
---------------------------------------------------------------------------
|
|
|
|
|
|
|
assert false report "Simulation sucessful" severity failure;
|
assert false report "Simulation sucessful" severity failure;
|
end process WaveGen_Proc;
|
end process WaveGen_Proc;
|
