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Line 6... |
--*
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--*
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--* @author: Daniel Köthe
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--* @author: Daniel Köthe
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--* @version: 1.0
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--* @version: 1.0
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--* @date: 2007-11-11
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--* @date: 2007-11-11
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--/
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--/
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-- Version 1.1
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-- Bugfix
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-- added syncronisation registers opb_fifo_flg_int_r[0,1] to prevent
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-- metastability
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity irq_ctl is
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entity irq_ctl is
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end irq_ctl;
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end irq_ctl;
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architecture behavior of irq_ctl is
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architecture behavior of irq_ctl is
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signal opb_fifo_flg_int : std_logic;
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signal opb_fifo_flg_int : std_logic;
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-- Sync to clock domain register
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signal opb_fifo_flg_int_r0 : std_logic;
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signal opb_fifo_flg_int_r1 : std_logic;
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signal opb_fifo_flg_reg : std_logic;
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signal opb_fifo_flg_reg : std_logic;
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begin -- behavior
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begin -- behavior
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opb_fifo_flg_int <= opb_fifo_flg when (C_ACTIVE_EDGE = '1') else
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opb_fifo_flg_int_r0 <= opb_fifo_flg when (C_ACTIVE_EDGE = '1') else
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not opb_fifo_flg;
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not opb_fifo_flg;
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irq_ctl_proc: process(rst, clk)
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irq_ctl_proc: process(rst, clk)
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begin
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begin
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if (rst = '1') then
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if (rst = '1') then
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opb_isr <= '0';
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opb_isr <= '0';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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-- sync to clock domain
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opb_fifo_flg_int_r1 <= opb_fifo_flg_int_r0;
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opb_fifo_flg_int <= opb_fifo_flg_int_r1;
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opb_fifo_flg_reg <= opb_fifo_flg_int;
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opb_fifo_flg_reg <= opb_fifo_flg_int;
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if (opb_ier= '1' and opb_fifo_flg_int = '1' and opb_fifo_flg_reg = '0') then
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if (opb_ier= '1' and opb_fifo_flg_int = '1' and opb_fifo_flg_reg = '0') then
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opb_isr <= '1';
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opb_isr <= '1';
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elsif (opb_isr_clr = '1') then
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elsif (opb_isr_clr = '1') then
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opb_isr <= '0';
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opb_isr <= '0';
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