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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use IEEE.numeric_std.all; -- conv_integer()
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use IEEE.numeric_std.all; -- conv_integer()
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library work;
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use work.opb_spi_slave_pack.all;
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entity opb_m_if is
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entity opb_m_if is
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generic (
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generic (
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C_BASEADDR : std_logic_vector(0 to 31) := X"00000000";
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C_BASEADDR : std_logic_vector(0 to 31) := X"00000000";
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C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
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C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
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C_USER_ID_CODE : integer := 0;
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C_USER_ID_CODE : integer := 0;
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opb_m_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0);
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opb_m_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0);
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-- enable/disable dma transfer
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-- enable/disable dma transfer
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opb_tx_dma_ctl : in std_logic_vector(0 downto 0);
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opb_tx_dma_ctl : in std_logic_vector(0 downto 0);
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-- base adress for transfer
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-- base adress for transfer
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opb_tx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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opb_tx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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opb_tx_dma_num : in std_logic_vector(15 downto 0);
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opb_tx_dma_num : in std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
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opb_tx_dma_done : out std_logic;
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opb_tx_dma_done : out std_logic;
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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-- write transfer
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-- write transfer
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-- read fifo an write to memory
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-- read fifo an write to memory
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opb_m_rx_req : in std_logic;
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opb_m_rx_req : in std_logic;
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opb_m_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0);
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opb_m_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0);
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-- enable/disable dma transfer
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-- enable/disable dma transfer
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opb_rx_dma_ctl : in std_logic_vector(0 downto 0);
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opb_rx_dma_ctl : in std_logic_vector(0 downto 0);
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-- base adress for transfer
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-- base adress for transfer
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opb_rx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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opb_rx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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opb_rx_dma_num : in std_logic_vector(15 downto 0);
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opb_rx_dma_num : in std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
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opb_rx_dma_done : out std_logic);
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opb_rx_dma_done : out std_logic);
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end opb_m_if;
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end opb_m_if;
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architecture behavior of opb_m_if is
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architecture behavior of opb_m_if is
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signal read_transfer : boolean;
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signal read_transfer : boolean;
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-- read transfer
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-- read transfer
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signal opb_tx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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signal opb_tx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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signal opb_tx_dma_en : std_logic;
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signal opb_tx_dma_en : std_logic;
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signal opb_tx_dma_num_int : std_logic_vector(15 downto 0);
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signal opb_tx_dma_num_int : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
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signal opb_tx_dma_done_int : std_logic;
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signal opb_tx_dma_done_int : std_logic;
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-- write transfer
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-- write transfer
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signal opb_rx_dma_en : std_logic;
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signal opb_rx_dma_en : std_logic;
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signal opb_rx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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signal opb_rx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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signal opb_rx_dma_num_int : std_logic_vector(15 downto 0);
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signal opb_rx_dma_num_int : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
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signal opb_rx_dma_done_int : std_logic;
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signal opb_rx_dma_done_int : std_logic;
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begin -- behavior
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begin -- behavior
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